AI Accelerator With Dual Clock Accumulators for Neural Network Processing
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Solution Overview
Problem
Existing artificial intelligence (AI) accelerators face challenges in efficiently performing deep learning operations due to the exponential increase in computation requirements and limitations in data communication between memory and processors, leading to degraded performance.
Innovation Solution
The proposed AI accelerator incorporates memory circuits, multiplication circuits, accumulative adder trees, and synchronized accumulators to perform accumulating calculations efficiently, optimizing performance by integrating processing and memory within a semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of layers in neural network is increased to improve AI performance, then AI performance is improved, but computation requirement increases exponentially
Solution Approach 1:
The patent segments the computation process into multiple processing channels (first processing channel and second processing channel) that operate in parallel. Each channel handles specific neural network operations independently, dividing the overall computation task into manageable segments that can be processed simultaneously, thereby reducing the computational burden on any single processing unit.
Solution Approach 2:
The patent introduces a time dimension by using different clock signals (first clock signal and second clock signal) to control different processing channels. This allows the system to process multiple operations across different time cycles, effectively adding a temporal dimension to the computation architecture to handle increased computational requirements.
2Adaptability or versatility
If general hardware system with separate memory and processor is used, then system flexibility is maintained, but data communication between memory and processor degrades performance
Solution Approach 1:
The patent merges the memory and processing units into a unified architecture where processing channels are directly coupled to memory circuits. This integration reduces the communication distance and latency between data storage and processing, eliminating the performance bottleneck associated with separate memory and processor systems while maintaining system flexibility through modular design.
3Productivity
If processing-in-memory device is used to improve data processing speed, then data processing speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the processing-in-memory device into multiple independent processing channels, each with its own multiplication circuit and adder tree. This segmentation allows the complex PIM operations to be distributed across multiple simpler units, reducing the complexity of any single processing element while maintaining high data processing speed through parallel operation.
Solution Approach 2:
The patent implements partial processing by handling different portions of data through separate processing channels at different time cycles. The first processing channel processes data during first clock cycles while the second processing channel processes data during second clock cycles, allowing the system to manage complexity by processing only partial data sets at any given time.
Data Source
AI summary
An artificial intelligence (AI) accelerator includes memory circuits configured to output weight data and vector data, a multiplication circuit/adder tree performing a multiplying/adding calculation on the weight data and the vector data to generate multiplication/addition result data, a first accumulator synchronized with an odd clock signal to perform an accumulative adding calculation on odd-numbered multiplication/addition result data of the multiplication/addition result data and a first latched data, and a second accumulator synchronized with an even clock signal to perform an accumulative adding calculation on even-numbered multiplication/addition result data of the multiplication/addition result data and a second latched data.