AI Accelerator Mesh Topology With Selective Diagonal Links

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Solution Overview

Problem

Existing AI model accelerators face challenges in balancing high reliability and performance with moderate complexity and cost, particularly in data transmission and processing efficiency, especially in fully connected and sparsely interconnected topologies.

Innovation Solution

A mesh topology is implemented with both fully connected and partially connected blocks, where nodes are connected to all orthogonally adjacent nodes and a set number of diagonally adjacent nodes, utilizing disjoint spanning trees for efficient data routing and operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fully connected topology is used to ensure high reliability and performance, then data transmission reliability is improved, but device complexity and cost increase

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidtopology complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The mesh topology is segmented into multiple blocks (first blocks with full connectivity and second blocks with partial connectivity). This segmentation allows the system to achieve high reliability in critical areas while reducing complexity in less critical areas, resolving the contradiction between reliability and complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the mesh topology are assigned different connectivity qualities. First blocks have full connectivity for high reliability, while second blocks have partial connectivity for reduced complexity. This local differentiation allows the system to optimize both reliability and complexity simultaneously

Inventive Principle:
Principle #3Local quality

2Productivity

If a fully connected topology is used to maintain high performance, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidtopology complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The topology is divided into blocks with different connectivity levels. First blocks maintain full connectivity for high processing speed, while second blocks use partial connectivity to reduce complexity, achieving a balance between productivity and complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of providing full connectivity to all blocks (excessive action), the system provides full connectivity only to first blocks where it is most needed, and partial connectivity to second blocks (partial action). This optimized approach maintains high processing speed while reducing overall complexity

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If more nodes are connected to increase reliability, then data transmission reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The mesh is segmented into blocks that can be manufactured independently with different connectivity requirements. This segmentation enables selective manufacturing - full connectivity for first blocks where reliability is critical, and reduced connectivity for second blocks where cost is a constraint

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different manufacturing qualities are applied to different regions. First blocks receive full connectivity for high reliability, while second blocks receive partial connectivity for cost-effectiveness. This local quality differentiation resolves the contradiction between reliability and manufacturing cost

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260037316A1Accelerator with mixed connectivity topology, electronic device and operation method thereof
Publication Date: 2026.02.05 SAMSUNG ELECTRONICS CO LTD
  • US20260037316A1 patent drawing
  • US20260037316A1 patent drawing
  • US20260037316A1 patent drawing

AI summary

An accelerator includes: switches having a mesh topology; and processing units connected to the switches, respectively, wherein the mesh topology comprises nodes corresponding to the switches, and edges configured to connect the nodes, and wherein the nodes comprise a given node that is connected to all of its orthogonally adjacent nodes in the mesh topology that are orthogonally adjacent to the given node, and connected to a set number of diagonally adjacent nodes among one or more its diagonally adjacent nodes in the mesh topology that are diagonally adjacent to the given node.