AI Accelerator Hardware for Nonlinear Function Evaluation
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Solution Overview
Problem
Deep learning neural network computations, particularly nonlinear functions, are resource-demanding and lead to long delays and high power consumption due to intensive workload in AI applications.
Innovation Solution
A system comprising a processor and an accelerator with specialized fixed-function hardware circuits for evaluating nonlinear functions, where the processor decodes math instructions and sends signals to the accelerator to evaluate nonlinear functions efficiently, using first and second evaluators for individual and composite functions respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If general-purpose processors are used for neural network computations, then system flexibility is maintained, but processing speed and power efficiency deteriorate due to intensive nonlinear function evaluations
Solution Approach 1:
The system is divided into two distinct parts: a general-purpose processor that handles control and data preparation, and a specialized accelerator that handles nonlinear function evaluations. This segmentation allows each component to be optimized for its specific function, achieving high processing speed in the accelerator while maintaining system flexibility through the processor.
Solution Approach 2:
The patent introduces an intermediary interface between the processor and accelerator that enables efficient communication and coordination. The processor prepares input data and sends control signals to the accelerator, which then performs the computationally intensive nonlinear function evaluations and returns results to the processor, effectively mediating the computational workload.
2Loss of time
If software-based nonlinear function evaluation is used, then device complexity is reduced, but processing time increases significantly from tens or hundreds of clock cycles
Solution Approach 1:
The patent replaces software-based nonlinear function evaluation (mechanical/system-level operation) with hardware-based evaluation using dedicated circuits. The accelerator incorporates specialized hardware circuits that can evaluate nonlinear functions in parallel, reducing processing time from tens or hundreds of clock cycles to just a few cycles, while accepting increased device complexity through the hardware accelerator.
3Use of energy by moving object
If resource-demanding nonlinear computations are performed, then computational accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters of nonlinear function evaluation by implementing hardware circuits with optimized precision. The accelerator uses fixed-point or floating-point arithmetic units designed specifically for neural network computations, maintaining computational accuracy while dramatically reducing power consumption compared to software-based approaches running on general-purpose processors.
Data Source
AI summary
A system includes an accelerator to accelerate the computations of nonlinear math functions. The accelerator includes a set of first evaluators and a set of second evaluators. Each of the first evaluators and the second evaluators is a fixed-function hardware circuit specialized for evaluating a respective nonlinear function. The system further includes a processor which decodes a math instruction in an instruction set, sends to the accelerator a signal identifying a nonlinear function corresponding to the math instruction, and receives an output of the nonlinear function from the accelerator. According to the signal, the accelerator evaluates the nonlinear function using one of the first evaluators. When the signal identifies the nonlinear function as a composite function, the accelerator additionally uses one of second evaluators on an output of the one first evaluator.