AI Accelerator Tile Parallelism for Neural Network Efficiency
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Solution Overview
Problem
The increasing depth of neural network models and large input data sizes, particularly in applications like medical image recognition and high-definition video recognition, lead to significant computing pressure and low processing efficiency, necessitating an acceleration solution.
Innovation Solution
An artificial intelligence accelerator with a control unit, computing engine, and group cache unit, capable of parallel processing and adaptation, splits input images into tiles, generates concurrent instructions, and performs parallel processing to reduce data migration and power consumption, while managing varying parallelism degrees across network layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the depth of neural network model is increased to meet application requirements, then the model's recognition capability is improved, but the computing amount significantly increases and processing efficiency decreases
Solution Approach 1:
The patent divides the neural network model into multiple network layers, and further divides input data into multiple tiles. Each tile is processed independently by computing units, enabling parallel processing across layers and tiles. This segmentation allows deep models to be processed efficiently by distributing computation across multiple parallel paths, resolving the contradiction between model depth and processing efficiency.
2Measurement precision
If the size of input data is increased to meet high image precision requirements, then the recognition accuracy is improved, but the computing pressure significantly increases
Solution Approach 1:
Large input images are divided into multiple smaller tiles, which are then processed in parallel by multiple computing units. This segmentation reduces the computing pressure on individual units while maintaining the ability to process high-resolution images, thus resolving the contradiction between image precision and computing pressure.
Solution Approach 2:
The patent introduces parallelism across multiple dimensions: parallel processing of multiple tiles, parallel processing across multiple network layers, and parallel computation within each tile. This multi-dimensional parallelism distributes the computational load, reducing computing pressure while maintaining high image precision processing capability.
3Productivity
If parallel processing is implemented to improve processing efficiency, then the processing speed is improved, but the device complexity increases
Solution Approach 1:
The accelerator is segmented into multiple computing units that can be configured to process different tiles and network layers. This modular segmentation enables parallel processing while keeping individual unit complexity manageable, as each unit handles a specific portion of the overall computation.
Solution Approach 2:
The computing units are designed with universal functionality to handle various operations across different network layers and tile types. This multi-functionality reduces overall device complexity by using identical or similar units for diverse tasks, rather than requiring specialized hardware for each function.
Data Source
AI summary
An artificial intelligence accelerator, a device, a chip, and a data processing method are provided. The artificial intelligence accelerator has a capability to respectively process data with a depth of a second quantity in parallel by using a first quantity of operation functions, and includes a control unit, a computing engine, a group control unit, and a group cache unit. The control unit is configured to parse a processing instruction for a target network layer in a neural network model to obtain a concurrent instruction, the computing engine is configured to perform parallel processing on a target input tile in the input data set according to the concurrent instruction to obtain target output data corresponding to the target input tile, and the group control unit is configured to store, by group, the target output data into at least one output cache of the group cache unit.