AI Chip Instruction Execution Locking Mechanism
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Solution Overview
Problem
Conventional CPU computing power is inadequate for handling the compute-intensive operations in neural network models, leading to inefficiencies in task scheduling for neural network processors.
Innovation Solution
A method and apparatus for an artificial intelligence chip that includes general-purpose and special-purpose execution components, where descriptive information for neural network models is received, analyzed, and specific operation instructions are sent to special-purpose execution components, which are locked and unlocked as needed to manage task execution efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host CPU continuously interacts with the neural network processor to implement task scheduling, then the task scheduling can be implemented, but the computing efficiency is reduced due to frequent interactions
Solution Approach 1:
The neural network processor is equipped with an independent instruction execution unit that can autonomously schedule and execute instructions without continuous CPU intervention. The processor itself manages task scheduling, resource allocation, and instruction flow control, enabling it to serve its own scheduling needs independently of the host CPU.
Solution Approach 2:
The system is divided into two independent functional parts: the host CPU for high-level control and the neural network processor with its own instruction execution unit for autonomous instruction scheduling. This segmentation allows the neural network processor to handle instruction scheduling internally, reducing the need for continuous CPU interaction while maintaining system coordination.
2Power
If conventional CPU is used for compute-intensive operations in neural network models, then the system is simple to operate, but the computing power is insufficient to meet requirements
Solution Approach 1:
An independent instruction execution unit is introduced as an intermediary between the host CPU and the computing units. This intermediary translates high-level instructions into detailed execution steps, manages data flow between memory and computing units, and handles scheduling autonomously, thereby enabling the CPU to focus on high-level operations while the intermediary manages the complexity of instruction execution.
3Power
If special-purpose processors are developed for neural networks, then the computing power is improved, but the device complexity increases
Solution Approach 1:
The neural network processor is designed with a universal instruction execution unit that can handle multiple types of neural network operations (convolution, pooling, activation functions, etc.) through a unified architecture. This multi-functional design allows the processor to maintain high computing power for various neural network tasks while avoiding the need for separate specialized hardware for each operation type.
Data Source
AI summary
Embodiments of the present disclosure disclose a method and apparatus for executing an instruction for an artificial intelligence chip. A specific embodiment of the method comprises: receiving descriptive information for describing a neural network model sent by a central processing unit, the descriptive information including at least one operation instruction; analyzing the descriptive information to acquire the at least one operation instruction; determining, for an operation instruction of the at least one operation instruction, a special-purpose execution component executing the operation instruction, and locking the determined special-purpose execution component; sending the operation instruction to the determined special-purpose execution component; and unlocking the determined special-purpose execution component in response to receiving a notification for instructing the operation instruction being completely executed.