3D AI Chip Layout With Interleaved Memory for Lower Power
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Solution Overview
Problem
The multi-layer semiconductor stack used for AI operations faces challenges in reducing power consumption due to long data travel distances between functional units.
Innovation Solution
An AI module with a checkered or striped pattern arrangement of processing units and memory units on semiconductor chips, utilizing near-field inductive coupling for wireless communication between stacked chips, reduces wire lengths and power consumption while allowing efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a multi-layer semiconductor stack is used to perform AI operations, then functional units can be provided, but the travel distance for data between functional units becomes long, preventing reduction in power consumption
Solution Approach 1:
The patent transitions from a conventional layered architecture to a three-dimensional volumetric arrangement where processing units and memory units are interleaved in space. This spatial reorganization allows data to access memory through multiple dimensional pathways (horizontal, vertical, and diagonal), significantly reducing the effective travel distance and enabling low-power AI operations
2Use of energy by moving object
If processing units and memory units are arranged in conventional layouts, then manufacturing is simplified, but the arrangement does not optimize for low power consumption in AI operations
Solution Approach 1:
The semiconductor device is segmented into distinct processing units and memory units that are independently arranged in an interleaved pattern. This segmentation allows each unit type to be optimized separately while maintaining close spatial proximity, achieving low power consumption without excessive manufacturing complexity
Solution Approach 2:
Different regions of the semiconductor device are assigned different functional qualities - processing units in some locations and memory units in others, arranged in an interleaved pattern. This local differentiation optimizes data access locally at each processing unit while maintaining overall system coherence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables AI-based operations with low power consumption, improved accuracy, and reduced chip size, while maintaining high operational speed and efficiency.
Implementation Method 1
The plurality of semiconductor chips are stacked on the base chip in an inverted manner, and communication units having coil shapes are disposed in the stacked semiconductor chips. The communication units transmit and receive data to and from each other through near-field inductive coupling.
Data Source
AI summary
An AI module includes a first semiconductor chip. The first semiconductor chip includes a plurality of operation blocks each of which performs a predetermined operation and a plurality of memory blocks each including memory. The plurality of operation blocks and the plurality of memory blocks are arranged in a checkered pattern or in a striped pattern in plan view.