AI Chip Data Buffer Address Generation for Versatile Matrix Access
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Solution Overview
Problem
AI chips lack versatility due to low versatility of the apparatus for address generation in the data buffer, which is tailored to specific matrices, limiting their ability to perform a variety of computations.
Innovation Solution
Implement a system with multiple address generating circuits and an address combining circuit to generate addresses for elements in matrices using functions floor(ax+b)×T, allowing for versatile address generation across different computations without increasing design complexity or size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If address generating circuits are customized for specific matrices, then computation accuracy is improved, but versatility deteriorates
Solution Approach 1:
The address generating circuit is designed to handle multiple matrix types and computation patterns through a unified architecture. By incorporating configurable parameters and a combination of first and second address generating circuits, the system can adapt to different matrix dimensions and computation requirements without requiring separate customized circuits for each matrix type, thus achieving both accuracy and versatility.
Solution Approach 2:
The address generating circuit employs dynamic configuration capabilities where parameters such as matrix dimensions, element positions, and address calculation formulas can be adjusted based on the specific computation task. This dynamic adaptability allows the same circuit to optimize address generation for different matrix types while maintaining computational accuracy through task-specific parameter settings.
2Adaptability or versatility
If multiple apparatuses for address generation are provided, then versatility is improved, but device complexity increases
Solution Approach 1:
Instead of providing multiple separate address generating apparatuses for different matrix types, the invention merges multiple address generation functions into a single unified circuit. This unified circuit contains both first address generating circuits for generating addresses of elements within a matrix and second address generating circuits for generating addresses of matrices themselves, combining what would otherwise require multiple independent apparatuses into one integrated solution.
Solution Approach 2:
The unified address generating circuit is segmented into functional modules including first address generating circuits for element-level address generation and second address generating circuits for matrix-level address generation. This segmentation allows each module to perform its specific function efficiently while the overall system maintains versatility through the coordination of these modular components, avoiding the complexity of multiple complete apparatuses.
3Adaptability or versatility
If area is increased to accommodate more address generating circuits, then versatility is improved, but area consumption increases
Solution Approach 1:
The address generating circuit achieves high versatility within a compact area by designing a universal circuit structure that can handle multiple matrix types and computation patterns. Through configurable parameters and the combination of first and second address generating circuits, the system provides multi-functional capability without requiring multiple separate physical apparatuses, thus maintaining low area consumption while achieving high adaptability.
Data Source
AI summary
Disclosed are an apparatus and a method for address generation, a data buffer, and an artificial intelligence chip. The apparatus includes address generating circuits, including N first address generating circuits and M second address generating circuits, where an n-th first address generating circuit generates a first address yn of each element in each of first matrices required for computations on an n-th first dimension according to yn=floor(anxn+bn)×Tn, and the first matrices are distributed along M second dimensions; and an m-th second address generating circuit generates a second address ym of each first matrix on an m-th second dimension according to ym=floor(amxm+bm)×Tm; and an address combining circuit generating an address for accessing each element in each first matrix by combining the second address of each first matrix on the M second dimensions and the first address of each element in each first matrix on N first dimensions.