AI Chip Parameter Storage Layout for Secure NPU Weight Deployment
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Solution Overview
Problem
Existing AI computing systems face challenges with high costs, performance bottlenecks, power consumption, and security risks due to the high computing power required, particularly in intelligent terminal devices, where neural network software code and weight parameters are vulnerable to theft and cracking when stored in off-chip DRAM.
Innovation Solution
Implementing an AI integrated chip with on-chip storage units, including a second on-chip storage unit to securely store critical neural network code and weight parameters, and using an OTP device to manage decryption keys, ensuring only the NPU can read and the CPU can write, thereby enhancing security and reducing bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If neural network code and weight parameters are stored in off-chip DRAM, then storage capacity is sufficient, but security level is low and vulnerable to theft and cracking
Solution Approach 1:
The patent divides the storage system into multiple segments: off-chip DRAM for bulk storage and on-chip storage units (first and second on-chip storage units) for secure storage of critical neural network code and weight parameters. This segmentation allows the system to maintain sufficient storage capacity while isolating sensitive data in secure on-chip locations that are difficult to access externally.
Solution Approach 2:
The patent implements a nested storage architecture where on-chip storage units are embedded within the AI computing apparatus, creating layers of protection. The second on-chip storage unit is specifically designed to store encrypted or protected neural network parameters, with access controlled through specific permission settings that require both read permission for NPU and write permission for CPU, effectively nesting security mechanisms within the storage hierarchy.
2Reliability
If all neural network code and weight parameters are stored in on-chip storage units, then security level is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies local quality by assigning different storage locations based on the security requirements of specific data. Critical neural network code and weight parameters are stored in the secure second on-chip storage unit with restricted access permissions, while less sensitive data can be stored in the off-chip DRAM. This localized security approach protects only what is necessary without making the entire system complex.
Solution Approach 2:
The patent implements partial action by storing only the most critical neural network parameters in the secure second on-chip storage unit, rather than all parameters. This selective approach provides adequate security for sensitive data while avoiding the complexity and cost of securing the entire storage system, balancing security needs with device simplicity.
3Reliability
If critical parameters are stored in on-chip storage unit with restricted access, then security is improved, but access speed and bandwidth requirements change
Solution Approach 1:
The patent merges the storage and processing functions by integrating the second on-chip storage unit directly with the NPU, allowing the NPU to access critical parameters without external memory interfaces. This integration maintains high access speed for authorized operations while the restricted permission model (read permission for NPU only) provides security without requiring complex access protocols that would slow down processing.
Data Source
AI summary
An AI computing apparatus includes an AI integrated chip and an off-chip memory. The AI integrated chip includes a CPU, an NPU, a first on-chip storage unit, and a second on-chip storage unit. Permission to allow only the NPU to read and permission to allow only the CPU to write are set in the second on-chip storage unit. The off-chip memory stores first neural network code and a first weight parameter that are associated with the NPU. The second on-chip storage unit stores second neural network code and a second weight parameter that are associated with the NPU.