AI Codebook Encoding for Secure High-Speed Intrachip Data Transfer

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Solution Overview

Problem

The rapid growth of data storage demand exceeds the capacity to store it, and transmission bandwidth is becoming a bottleneck, especially with the rise of quantum computing and increased processor complexity, where data transport between processors is costly and inefficient.

Innovation Solution

Implementing AI-driven encoding techniques to identify patterns in data and use a pre-trained reference codebook for encoding and decoding, reducing the data size by 60-80% and enabling high-speed intrachip communications with low latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional data compression algorithms are used to reduce data size, then storage capacity is improved, but transmission latency increases significantly

Engineering Contradiction:
Improvedata sizeVSAvoidtransmission latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs preliminary encoding of data into a compact format before transmission. The encoder converts data into a condensed representation that can be quickly transmitted, avoiding the need for compression/decompression operations during critical transmission paths, thus reducing latency while maintaining compact data size.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention extracts only the essential and frequently accessed data elements for transmission between processors, rather than transmitting complete datasets. This selective extraction reduces both data size and transmission time, resolving the contradiction between compactness and speed.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If more processors are added to increase processing power, then computational capability is improved, but data transport cost and bandwidth requirements increase

Engineering Contradiction:
Improveprocessing powerVSAvoiddata transport volume
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system merges data representation across multiple processors by maintaining a unified encoded data format that can be efficiently shared and accessed. This consolidation reduces redundant data transmission between processors, allowing increased processing power without proportional increases in data transport volume.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Instead of transmitting large volumes of actual data between processors, the system transmits compact references or pointers to encoded data stored in shared memory. This copying approach allows multiple processors to access the same data efficiently without duplicating the full data payload, reducing bandwidth requirements while supporting high processing power.

Inventive Principle:
Principle #26Copying

3Productivity

If data is transmitted in high volume between processors, then processing capability is improved, but transmission bandwidth becomes a bottleneck

Engineering Contradiction:
Improveprocessing capabilityVSAvoidtransmission bandwidth
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The system changes the parameter of data representation from full-resolution data to compact encoded forms with references. This parameter transformation dramatically reduces the amount of data that needs to be transmitted between processors, enabling high processing capability without bandwidth bottlenecks.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention segments data into encoded portions with references, where only essential metadata and pointers are transmitted between processors while the actual data resides in shared storage. This segmentation allows processors to operate at high capability levels while minimizing transmission bandwidth requirements.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12591545B2System and method for securing high-speed intrachip communications
Publication Date: 2026.03.31 ATOMBEAM TECH INC
  • US12591545B2 patent drawing
  • US12591545B2 patent drawing
  • US12591545B2 patent drawing

AI summary

A system and method for securing high-speed communications between processing units on computer chips, wherein a training data set is used to find patterns and associated smaller indices, or codewords, which are stored in a reference codebook library, and where reconstruction and deconstruction algorithms are used to encode and decode data as it is received. The codebook and algorithms may be stored in the firmware of a semiconductor which enable reduced resources and cost when transmitting data between or among devices that utilize such semiconductors.