AI Compiler Instruction Scheduling With Parallel Breadth-Backtracking Search
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Solution Overview
Problem
Existing modulo scheduling algorithms in AI compilers face poor scheduling performance due to limited instruction search space expansion and lack of parallel processing, leading to inefficient instruction scheduling and slow execution times.
Innovation Solution
A method combining breadth-first search and backtracking search algorithms, performed in parallel through multiple threads, to expand the instruction search space and improve scheduling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If backtracking search algorithm is used for instruction scheduling, then scheduling can be performed sequentially, but the instruction search space is limited and scheduling performance is poor
Solution Approach 1:
The patent segments the instruction scheduling problem into multiple independent search tasks by dividing the instruction sequence into different ranges. Each thread handles a specific segment of instructions with its own search space, allowing parallel exploration of scheduling possibilities without overwhelming a single search process. This segmentation enables broader search space coverage while maintaining manageable complexity per thread.
Solution Approach 2:
The patent introduces parallelism as a new dimension by implementing multi-threaded search. Instead of sequentially exploring the search space in one dimension, multiple threads simultaneously explore different regions of the search space in parallel dimensions. This dimensional expansion dramatically increases the effective search capacity and improves scheduling performance by examining more possibilities within the same time frame.
2Speed
If backtracking search algorithm is used for instruction scheduling, then memory usage is controlled, but parallel processing is not supported and scheduling speed is slow
Solution Approach 1:
The patent divides the instruction scheduling task into multiple segments that can be processed in parallel by different threads. Each thread manages its own subset of instructions and search space, enabling simultaneous processing without requiring complex inter-thread coordination. This segmentation approach achieves parallel processing while keeping each thread's memory footprint manageable.
Solution Approach 2:
The patent creates multiple independent copies of the search mechanism, with each thread having its own search context, data structures, and state. This copying approach enables true parallel processing where each thread operates independently without shared state conflicts, dramatically increasing scheduling speed while avoiding the complexity of shared memory management and synchronization protocols.
3Adaptability or versatility
If core loop is expanded multiple times in modulo scheduling, then more instructions can be scheduled, but the number of instructions and search space expand exponentially
Solution Approach 1:
The patent segments the expanded core loop instructions into multiple smaller groups that can be processed in parallel. Instead of treating the exponentially growing instruction set as a single large problem, each thread handles a manageable subset, maintaining adaptability and scheduling coverage while preventing any single search process from being overwhelmed by exponential search space growth.
Solution Approach 2:
The patent addresses exponential search space growth by introducing parallel processing dimensions. Rather than sequentially exploring an exponentially expanding search space in one dimension, multiple threads simultaneously explore different regions in parallel dimensions. This transforms the complexity from exponential sequential search to linear parallel search, maintaining broad scheduling coverage while controlling effective search complexity.
Data Source
AI summary
A method for scheduling an instruction includes acquiring a first instruction sequence including N instructions and scheduling information being a scheduling parameter required for performing a scheduling operation on the N instructions; performing breadth search processing on the scheduling information and first M instructions among the N instructions based on a breadth search algorithm, to obtain L sub-scheduling sets, each sub-scheduling set comprising scheduling results of the first M instructions, and 1≤M<N; performing backtracking search processing in parallel on the scheduling information and remaining N-M instructions among the N instructions based on a backtracking search algorithm through L first threads in the L sub-scheduling sets, to obtain target scheduling results of the N instructions, the sub-scheduling sets corresponding one-to-one to the first threads; and generating a target code program based on the target scheduling results, the target code program being configured for scheduling the instructions.