AI Processor Core Warm-Up Instruction for Voltage Stability
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Solution Overview
Problem
Artificial intelligence chips face challenges in maintaining high computing power while avoiding sudden changes in power consumption and voltage fluctuations, which can lead to circuit damage and incorrect computing results.
Innovation Solution
A data processor core with a control unit that generates a warm-up instruction to gradually transition computing unit arrays from an idle state to a computing state, performing read and compute operations, thereby reducing abrupt power changes and maintaining stable voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the computing unit array directly transitions from idle state to computing state, then the computing power is quickly activated, but sudden power consumption changes and voltage fluctuations occur causing circuit damage and incorrect computing results
Solution Approach 1:
The patent introduces a warm-up instruction that is executed before the actual computing instruction. This warm-up instruction performs preliminary read operations and computing operations to gradually activate the computing unit array, preventing sudden power consumption changes and voltage fluctuations that would otherwise cause circuit damage and incorrect computing results.
Solution Approach 2:
The patent segments the transition process into distinct phases: a warm-up phase executed by the computing unit array in response to the warm-up instruction, and a subsequent computing phase executed in response to the actual computing instruction. This segmentation allows the system to gradually reach full computing power rather than activating all units simultaneously.
2Speed
If the computing unit array directly transitions from idle state to computing state, then the response time is reduced, but voltage fluctuations occur causing circuit damage
Solution Approach 1:
The warm-up instruction performs preliminary operations that gradually activate the computing unit array before the actual computing work begins. This preliminary action prevents sudden voltage fluctuations and circuit damage while maintaining relatively fast response time, as the warm-up phase is integrated into the instruction execution pipeline rather than being a separate external preparation step.
3Productivity
If the computing unit array directly transitions from idle state to computing state, then the computing efficiency is improved, but power consumption changes abruptly
Solution Approach 1:
The patent segments the power consumption profile into a gradual warm-up phase followed by a sustained computing phase. The warm-up instruction causes the computing unit array to gradually increase activity levels, resulting in smooth power consumption transitions rather than abrupt changes, while still achieving high computing efficiency in the subsequent phase.
Solution Approach 2:
The warm-up instruction performs preliminary computing operations that gradually activate the computing unit array. This preliminary action establishes a stable power consumption baseline before the main computing work begins, preventing abrupt power consumption changes while maintaining high computing efficiency during the actual computation.
Data Source
AI summary
A data processor core, which relates to a field of artificial intelligence technology, and in particular to a field of integrated circuit technology and a field of chip technology. The processor core includes: a control unit configured to generate a warm-up instruction in response to detecting a computing instruction to be processed; and a computing unit array including at least one computing unit sub-array, wherein the computing unit sub-array is configured to: receive the warm-up instruction configured to instruct the computing unit sub-array to perform a read operation and a computing operation; enter a warm-up state according to the warm-up instruction; and switch from the warm-up state to a computing state in response to receiving a target instruction corresponding to the computing instruction to be processed. The present disclosure further provides a data processor, a method of processing data, an electronic device, and a storage medium.