AI Hardware Accelerator Testing via Compressed Pattern Segmentation
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Solution Overview
Problem
Conventional test generation techniques are inadequate for system-level testing of AI hardware accelerators due to excessive time and space requirements, making it difficult to achieve effective test coverage and error analysis.
Innovation Solution
A method that reduces test generation, result prediction, and execution times by using a daisy chain of function codes for hardware execution and simulated execution in software, allowing for efficient test coverage and error analysis through targeted data tracing and printing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test generation techniques are used for system-level testing of AI hardware accelerators, then test coverage can be achieved, but test generation time and space requirements become prohibitively large
Solution Approach 1:
The patent segments the testing process into two distinct phases: (1) a compression phase that generates compressed test patterns and expected results using software simulation, and (2) an execution phase that applies these compressed patterns to the hardware accelerator. This segmentation allows the time-consuming simulation to be done once on reduced data, rather than repeatedly on full test data, thereby reducing overall test generation time while maintaining comprehensive test coverage.
Solution Approach 2:
The patent creates a software-based copy or model of the AI hardware accelerator's function codes. This software model is used to pre-compute expected test results and generate compressed test patterns without requiring actual hardware execution. By copying the functional behavior in software, the system can prepare test data efficiently and then validate the hardware accelerator against these pre-computed expectations, significantly reducing test generation time.
2Reliability
If conventional test generation techniques are used for system-level testing of AI hardware accelerators, then test coverage can be achieved, but the space and resources required become prohibitively large
Solution Approach 1:
The patent extracts and separates the essential testing functionality from the full test data set. By identifying and extracting only the critical function codes and their expected behaviors, the system creates a condensed software model that captures the necessary test coverage requirements. This extraction process removes unnecessary data elements, resulting in compressed test patterns that maintain test effectiveness while requiring significantly less storage space and resources.
Solution Approach 2:
The patent transforms the test data from its original full-resolution format into a compressed representation by changing key parameters. The compression process modifies data granularity, selecting only representative test cases and encoding expected results in a condensed format. This parameter transformation reduces the quantity of test data needed while preserving the ability to achieve comprehensive test coverage when the compressed patterns are executed against the hardware accelerator.
3Measurement precision
If error detection is performed in AI hardware accelerator testing, then errors can be identified, but error analysis and printing become infeasible due to the large size of test data
Solution Approach 1:
The patent performs preliminary computation of expected test results using the software model before actual hardware testing. By pre-calculating what the correct outputs should be for each compressed test pattern, the system establishes a baseline for error detection. When hardware execution produces results, comparison against these pre-computed expectations enables precise error identification without requiring complex analysis of large data sets, as the expected outcomes are already determined in advance.
Data Source
AI summary
Methods, system, and computer program product are disclosed for enhanced system level testing of an AI hardware accelerator comprising Artificial Intelligence (AI) primitives. The system level testing provides uncompromised test coverage of the AI hardware accelerator while enabling efficient and effective testing performance. Enhanced test data generation, result prediction, and test execution are provided for system level testing of AI hardware accelerator including the AI primitives.