AI Hardware Architecture with Segmented Engines for Logic Utilization
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Solution Overview
Problem
Current AI processing technologies, such as GPUs and TPUs, are inefficient in utilizing logic for AI tasks, with only one-third of GPU logic used, and require significant software work for data reshaping and job splitting, while CPU and DSP solutions are not suitable for AI pipeline engineering.
Innovation Solution
A hardware architecture that treats AI work as 5D tensors, dividing tasks into groups and waves, utilizing a host, frontal, parietal, renderer, occipital, and temporal engines with configurable parietal engines and stream perceptron processors for efficient processing and data compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If GPU is used for AI processing, then computational power is improved, but logic utilization efficiency deteriorates (only one-third of GPU logic is used)
Solution Approach 1:
The patent segments AI processing into distinct functional stages: data preprocessing in the frontal engine, parallel computation in multiple parietal engines, result aggregation in the occipital engine, and output processing in the temporal engine. This segmentation allows each engine to be optimized for its specific function, improving overall logic utilization efficiency while maintaining high computational power through parallel processing across multiple engines.
2Productivity
If TPU is used for AI processing, then computation and data reuse are improved, but software complexity increases (requires more software work to reshape data layout, split jobs, and send to compute core)
Solution Approach 1:
The hardware architecture incorporates dedicated functional engines that automatically perform data reshaping, job splitting, and result aggregation without requiring extensive software intervention. The frontal engine handles input data preparation, parietal engines perform parallel computation, the occipital engine aggregates results, and the temporal engine manages output - all through hardware-based automation rather than software orchestration, reducing software complexity while maintaining high productivity.
3Adaptability or versatility
If CPU or DSP is used for AI processing, then general-purpose computing is maintained, but suitability for AI pipeline engineering deteriorates
Solution Approach 1:
The patent creates a multi-functional AI processing system where the frontal engine handles diverse input preprocessing tasks, parietal engines perform various parallel computations, the occipital engine aggregates different types of results, and the temporal engine manages diverse output formats. This universal architecture maintains adaptability for different AI workloads while achieving high productivity through specialized functional engines optimized for AI pipeline operations.
Data Source
AI summary
A hardware architecture that may include: a host, a frontal engine, a parietal engine, a renderer engine, an occipital engine, a temporal engine, and a memory. The frontal engine may obtain a 5D tensor from the host and divide it into several groups of tensors. These groups of tensors may be sent or transmitted to the parietal engine, and the parietal engine may take the groups of tensors to further divide them into several tensors. The parietal engine may send these tensors to the renderer engine for execution and may send a partial amount of tensors to the occipital engine. The occipital engine may accumulate the partial amount of tensors and may execute them. The occipital engine may send the output feature as the final tensor to the temporal engine. The temporal engine may compress the final tensor before storing or saving it to the memory.