AI Node Power Control via Chip Grouping and BMC Policy
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Solution Overview
Problem
Existing power regulation methods for traditional servers are not applicable to AI computing nodes, as they fail to effectively manage the significant power consumption of computing chips, leading to inefficient power control.
Innovation Solution
A power regulation and control method involving a baseboard management controller (BMC) that acquires chip power values, groups computing chips, and adjusts power limit values based on a predefined policy to maintain energy efficiency within a target range, ensuring the AI computing node operates within optimal power parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional server power regulation methods are used (controlling internal memory, CPU, fan), then power control works for traditional servers, but it is ineffective for AI computing nodes where computing chips consume the majority of power
Solution Approach 1:
The patent changes the control parameter from traditional components (CPU, memory, fan) to computing chip power consumption. It introduces new parameters including chip power values, power limit values, grouping levels, and energy efficiency values to effectively regulate power in AI computing nodes where chips dominate power consumption.
Solution Approach 2:
The patent segments computing chips into different groups based on their power consumption characteristics. By dividing chips into multiple groups with different power limit values, it enables differentiated power management that adapts to the specific power distribution patterns in AI computing nodes.
2Loss of energy
If power limit values are reduced to lower power consumption, then power usage decreases, but energy efficiency of computing chips deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors actual power consumption and energy efficiency values, compares them against target ranges, and dynamically adjusts power limit values. This closed-loop control ensures power reduction while maintaining energy efficiency within acceptable boundaries.
Solution Approach 2:
The patent introduces dynamic power management where power limit values are not fixed but adjusted in real-time based on actual power consumption patterns and energy efficiency measurements. The system can flexibly modify power limits across different chip groups to optimize the balance between power savings and performance.
3Ease of operation
If uniform power limits are applied to all computing chips, then control is simple, but it cannot optimize energy efficiency for different chip power characteristics
Solution Approach 1:
The patent applies different power limit values to different groups of computing chips based on their local power consumption characteristics. Instead of a uniform approach, each chip group receives tailored power management parameters that match its specific operational profile, optimizing overall system efficiency.
Solution Approach 2:
The patent applies partial power limiting strategies where not all chips are subjected to the same degree of power restriction. By selectively applying different power limit levels to different chip groups, it achieves effective power management without overly constraining any single group's performance.
Data Source
AI summary
A power regulation and control method, apparatus and device, and a readable storage medium. The method disclosed in the present application includes: in response to a node power value of an artificial intelligence (AI) computing node being greater than a warning power value, acquiring, by a baseboard management controller (BMC), chip power values of computing chips in the AI computing node; obtaining a grouping result by grouping, according to the chip power values of the computing chips, the computing chips; and in response to the node power value being greater than a power capping value, querying a power regulation and control policy corresponding to the grouping result, and regulating power limit values of the computing chips according to the power regulation and control policy, such that a sum of all the power limit values is in a target range, where the warning power value is less than the power capping value, the power regulation and control policy is preset on the basis of the target range, and the target range is used for regulating and controlling energy efficiency values of the computing chips in the AI computing node.