AI Power Management in Multi-Die Stacks for Thermal Limits
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Solution Overview
Problem
The thermal design power (TDP) envelope of processors is limited by insufficient thermal dissipation in multi-die stacks, which restricts their operating speed due to the close proximity of high-performance dies, leading to potential overheating.
Innovation Solution
Incorporating artificial intelligence (AI) architecture circuitry within the CPU dies to manage power consumption by dynamically adjusting operational parameters such as power states, voltages, and frequencies, and integrating through silicon vias (TSVs) for efficient data transfer, thereby reducing thermal concentration and enhancing power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple high-performance dies are stacked in close proximity to increase processing power, then productivity is improved, but temperature increases due to insufficient thermal dissipation
Solution Approach 1:
The processor is divided into multiple separate dies stacked vertically, with each die being a distinct functional unit. This segmentation allows independent thermal management for each die while maintaining high processing power through parallel operation of multiple dies.
Solution Approach 2:
The processor transitions from a traditional planar (2D) layout to a vertical (3D) stacked architecture. By arranging dies in the vertical dimension rather than spreading them horizontally, the design achieves higher processing power density while enabling improved thermal dissipation through the vertical stacking configuration.
2Volume of moving object
If multiple dies are stacked in vertical alignment to reduce form factor, then volume is reduced, but temperature increases due to thermal concentration
Solution Approach 1:
The processor adopts a vertical 3D stacked architecture instead of a horizontal 2D layout, compressing the form factor in the horizontal plane while managing thermal issues through the vertical arrangement and associated thermal management structures.
Solution Approach 2:
Thermal management structures are introduced as intermediary components between the stacked dies to facilitate heat dissipation. These structures act as mediators that transfer and distribute thermal energy from the high-density die stack to the surrounding environment, preventing thermal concentration despite the compact vertical arrangement.
3Use of energy by moving object
If AI architecture circuitry is added to manage power consumption dynamically, then power management is improved, but device complexity increases
Solution Approach 1:
The AI architecture circuitry is integrated into the existing processor dies, serving multiple functions including workload inference, power management decisions, and coordination with the power management engine. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while achieving dynamic power consumption management.
Solution Approach 2:
The processor incorporates AI circuitry that enables the system to autonomously monitor its own workload and power consumption, making real-time adjustments without external intervention. This self-service capability allows dynamic power management while keeping the added complexity contained within the processor itself.
Data Source
AI summary
Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example integrated circuit (IC) package includes a computer processor unit (CPU) die, a memory die, inference engine circuitry within the CPU die, the inference engine circuitry to infer, based on a first machine learning model, a workload for at least one of the CPU die or the memory die, and power management engine circuitry within the CPU die, the power management engine circuitry distinct from the inference engine circuitry, the power management engine circuitry to adjust, based on a second machine learning model different than the first machine learning model, operational parameters associated with the at least one of the CPU die or the memory die, the inferred workload to be an input to the second machine learning model.