Low-Precision AI Processor With 4-Bit Systolic Array Quantization

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Solution Overview

Problem

Conventional processors face inefficiencies in handling the complex algorithms and data-intensive workflows of AI processing due to their architecture and instruction sets optimized for traditional computing tasks, failing to meet the demands of AI workloads efficiently.

Innovation Solution

An AI-accelerating processor with a systolic array where at least 90% of multipliers are limited to 4-bit or lower input precision, combined with memory for storing values in FP16 or higher precision, to perform machine learning operations efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional processors are used for AI tasks, then general-purpose computation capability is maintained, but computational efficiency and power consumption are suboptimal

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The processor is segmented into specialized components: a systolic array for parallel matrix operations, quantization units for precision conversion, and separate memory structures for different precision formats. This segmentation allows each component to be optimized for its specific function, dramatically improving computational efficiency for AI workloads while reducing overall power consumption through targeted optimization rather than general-purpose design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically changes precision parameters by converting high-precision floating-point values to low-precision quantized values during computation. The quantization unit transforms FP16/FP32 data into integer formats (INT8, INT4, INT2), allowing the systolic array to perform computations at lower precision with reduced power consumption while maintaining sufficient accuracy for AI inference tasks.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If high-precision processing is used throughout, then computational accuracy is maintained, but processing speed and efficiency decrease

Engineering Contradiction:
Improvecomputational accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

Different precision levels are applied to different parts of the computational pipeline based on local requirements. The input memory maintains high precision (FP16/FP32) for accurate data storage, the quantization unit converts to low precision (INT8/INT4/INT2) for fast computation in the systolic array, and results are processed accordingly. This local quality approach ensures accuracy where needed while maximizing speed where possible.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The precision format is made dynamic rather than static. The system can switch between high-precision and low-precision modes depending on the computational stage and requirements. Data flows through the pipeline with precision being adjusted dynamically - high precision for input/storage, low precision for computation, enabling both accuracy and speed optimization.

Inventive Principle:
Principle #15Dynamics

3Productivity

If low-precision processing is used, then power consumption is reduced and speed is improved, but computational precision may be insufficient

Engineering Contradiction:
Improveprocessing speedVSAvoidcomputational precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

Quantization is performed as a preliminary action before computation. The quantization unit pre-processes high-precision input data by converting it to low-precision quantized values that are then fed into the systolic array. This preliminary conversion enables the computation stage to operate at full speed with low power consumption while the quantization process itself ensures that precision requirements are met through proper quantization algorithms and scaling.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12632219B2Quantization and low precision AI processor
Publication Date: 2026.05.19 MATX INC
  • US12632219B2 patent drawing
  • US12632219B2 patent drawing
  • US12632219B2 patent drawing

AI summary

A system may include an integrated circuit for an artificial-intelligence-accelerating (AI-accelerating) processor. The system may retrieve a set of values in a first precision format, the set of values associated with a machine learning model. The system may quantize the set of values to generate a set of quantized values in a second precision format. The system may perform computations of the set of quantized values using a systolic array of AI-accelerating processor. In some embodiments, at least 90% of the multipliers in the systolic array are limited to 4-bit or lower input precision.