AI Processor Memory Manager Slicing Neural Network Data

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Solution Overview

Problem

Current AI processor architectures for neural networks face inefficiencies in data processing and memory management, leading to suboptimal performance and high power consumption, particularly when handling large data sets with varying weight sizes.

Innovation Solution

The proposed AI processor features multiple clusters of arithmetic logic units with a scheduler and memory manager that slice data sets into chunks, broadcasting instructions across clusters for parallel processing, and dynamically switch between frame and channel sub-layering based on data and weight sizes, optimizing memory access and computation distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If data sets are processed using traditional AI processor architectures, then computation can be performed, but power consumption is high and processing efficiency is low due to excessive data movement

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing efficiency
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The data set is divided into multiple data chunks that are distributed across multiple clusters for parallel processing. Each cluster processes a specific chunk independently, reducing the total data movement required across the system while maintaining high processing throughput through concurrent operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The architecture introduces a new dimension of parallelism by organizing processing units into multiple clusters that can simultaneously handle different data chunks. This multi-dimensional parallel processing approach increases productivity without proportionally increasing power consumption, as each cluster operates independently with localized data access.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If data sets are sliced into chunks and distributed across clusters, then parallel processing efficiency increases, but system complexity increases due to memory management requirements

Engineering Contradiction:
Improveparallel processing efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A memory manager component is introduced as an intermediary that handles the complexity of data chunk distribution, cluster coordination, and result aggregation. This centralized memory management layer simplifies the overall system architecture by providing a unified interface for data flow control, reducing the complexity burden that would otherwise be distributed across multiple components.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If dynamic switching between frame and channel sub-layering is implemented, then adaptability to different neural network types improves, but control complexity increases

Engineering Contradiction:
Improveadaptability to neural network typesVSAvoidcontrol complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system dynamically switches between frame sub-layering and channel sub-layering modes based on the specific neural network type and data characteristics being processed. This dynamic adaptability allows the architecture to optimize performance for different workloads (e.g., image processing vs. sequence processing) while the underlying memory manager handles the complexity of mode switching transparently.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20230120227A1Method and apparatus having a scalable architecture for neural networks
Publication Date: 2023.04.20 ROVIERO INC
  • US20230120227A1 patent drawing
  • US20230120227A1 patent drawing
  • US20230120227A1 patent drawing

AI summary

An artificial intelligence processor can optimize the usage of its neural network to process a data set more efficiently. The artificial intelligence processor can have a neural network of multiple arithmetic logic units each having one or more computing engines and a local arithmetic memory divided into a set of clusters arranged into a node ring. A scheduler with a local scheduler memory for each cluster. An advanced extensible interface can read a data set model from an external memory in a single data read. A memory manager can control the node ring. When a data size of the data set is larger than a processing model layer for processing the data set, the memory manager can slice the data set into data set chunks. The memory manager can assign a data set chunk to a data cluster. The memory manager can broadcast channel instructions from the processing model layer to every cluster. The memory manager can process the data set chunk in the data cluster according to the channel instructions of the processing model. Alternately, when the data size of the data set is smaller than the processing model layer, the memory manager can slice the processing model layer into channel chunks. The memory manager can assign a channel chunk to a channel cluster. The memory manager can broadcast the data set to every cluster. The memory manager can process the data set chunk according to channel instructions of the channel chunk.