AI Test Vector Generation for Logic Verification Coverage
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Solution Overview
Problem
Circuit designs are highly complex and expensive to fabricate, with logical verification processes being difficult due to limited simulation cycles, vast state spaces, and potential biases or errors from human functional engineers, leading to costly bugs discovered after fabrication.
Innovation Solution
A computer-implemented method using an AI model to generate structured test vector sequences, which includes training a model for a specific design under test, generating control vectors, and using generators to create targeted test vectors to stimulate the DUT, with an output analysis module to characterize the results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If human functional engineers manually design test vectors, then the verification process can be completed within timeline requirements, but the state space coverage is limited and errors of omission occur
Solution Approach 1:
The system performs preliminary analysis of the design under test to automatically generate a comprehensive state space model before test vector creation. This preliminary action defines all possible states and transitions, ensuring complete coverage without relying on manual enumeration, thereby resolving the contradiction between time constraints and coverage completeness.
Solution Approach 2:
An automated test generation system acts as an intermediary between the design under test and the verification process. This intermediary automatically translates the state space model into structured test vector sequences, eliminating human bias and errors while maintaining timeline requirements through algorithmic efficiency.
2Reliability
If the state space is fully exhaustively tested, then complete verification coverage is achieved, but the simulation cycles required exceed timeline requirements
Solution Approach 1:
The vast state space is segmented into manageable components through automatic hierarchical decomposition. The system divides the overall state space into sub-state spaces corresponding to different functional modules, allowing efficient exploration of each segment while maintaining complete coverage through systematic composition, thereby reducing total simulation cycles required.
Solution Approach 2:
The system dynamically changes simulation parameters based on state space analysis results. By identifying critical states and transitions through automated modeling, the system adjusts simulation depth and breadth parameters to focus computational resources on high-risk areas, achieving complete verification coverage within timeline constraints.
3Ease of manufacture
If manual test design is used, then the verification process is simpler to implement, but biases and errors are introduced in defining the state space
Solution Approach 1:
The test generation system performs self-service by automatically analyzing the design under test and generating its own state space model without human intervention. The system extracts functional specifications directly from design documentation and autonomously defines all states and transitions, eliminating human bias and errors while maintaining implementation simplicity through automated workflows.
Solution Approach 2:
The manual mechanical process of state space definition by engineers is replaced with an automated computational system. The automated system uses algorithmic analysis to define the state space with precision, substituting human cognitive processes with deterministic computational methods that eliminate biases and errors while maintaining ease of implementation through standardized automation.
Data Source
AI summary
A computer implemented system for testing an electric circuit includes training an artificial intelligence (AI) model for a specific design under test (DUT) and generating at least one control vector using the AI model and providing the at least one control vector to at least one generator. The generator generates a set of structured test vector sequences. The DUT is stimulated using the set of structured test vector sequences and produces an output from the DUT. A set of output metrics characterizing the output using an output analysis module.