Antenna-in-Package PCB Shielding for Thin Low-Warpage Modules
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Solution Overview
Problem
Current antenna-in-package (AiP) devices fail to meet the requirements of reduced interface pitches, higher interface pin counts, reduced thickness, tight warpage control, and higher integration needed for cutting-edge cellular technologies and smaller device sizes.
Innovation Solution
The integration of semiconductor systems and antennas into a single package, utilizing a System-in-Package (SiP) module and antenna Printed Circuit Board (PCB) with advanced manufacturing processes such as singulation, encapsulation, and conductive layer formation, allows for higher pin counts, reduced thickness, and improved warpage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If antenna-in-package devices are integrated into smaller form factors, then device size is reduced, but manufacturing precision and warpage control become more difficult
Solution Approach 1:
The patent divides the antenna-in-package device into separate functional modules including RF front-end components, antenna elements, and packaging structures that are manufactured independently and then integrated. This segmentation allows each module to be optimized and manufactured separately with appropriate tolerances, reducing cumulative warpage issues while achieving compact overall device size.
Solution Approach 2:
The patent employs parameter changes in the packaging materials and structural design, including using low-expansion coefficient materials, adjusting layer thickness ratios, and modifying interconnection structures to compensate for thermal and mechanical stresses. These parameter adjustments enable tight warpage control in the reduced-form-factor device.
2Adaptability or versatility
If interface pin count is increased for higher integration, then device functionality is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar two-dimensional interconnection to three-dimensional vertical stacking architecture. Multiple interface pins and connections are arranged in vertical layers rather than spreading horizontally, enabling high pin counts and integration levels while maintaining manageable manufacturing complexity through standardized vertical interconnect processes.
Solution Approach 2:
The patent implements nested packaging structures where smaller functional modules with their own interconnections are embedded within larger package layers. This nesting approach allows multiple interface pins to be organized in hierarchical groups, reducing the complexity of routing and connection management while achieving high integration.
3Length of stationary object
If substrate thickness is reduced for smaller devices, then device footprint is decreased, but structural strength and reliability are compromised
Solution Approach 1:
The patent uses composite material structures in the substrate design, combining multiple layers of materials with complementary properties including high-strength support layers, low-expansion dielectric layers, and flexible interconnection layers. This composite approach provides the necessary structural strength and warpage resistance even in reduced-thickness substrates.
Solution Approach 2:
The patent applies local quality enhancement by providing selective reinforcement at critical locations within the substrate, such as adding support pillars, strengthening interconnection regions, or using thicker material only where mechanical strength is most needed. This allows overall substrate thickness to be reduced while maintaining strength at critical points.
Data Source
AI summary
A semiconductor device has a PCB with an antenna and a semiconductor package mounted onto the PCB. An epoxy molding compound bump is formed or disposed over the PCB opposite the semiconductor package. A first shielding layer is formed over the PCB. A second shielding layer is formed over the semiconductor package. A board-to-board (B2B) connector is disposed on the PCB or as part of the semiconductor package. A conductive bump is disposed between the semiconductor package and PCB.