Interconnect Air-Cap Structure for RC Delay and Cross-Talk
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Solution Overview
Problem
As feature sizes shrink in advanced semiconductor manufacturing, the parasitic capacitance between metal interconnects in high-density integrated circuits increases, leading to RC delay and cross-talk, necessitating improved interconnect structures.
Innovation Solution
Incorporation of air gaps between conductive features by selective deposition of inhibitor caps followed by deposition of dielectric materials to form air caps, reducing coupling capacitance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are shrunk to increase integration density, then the number of metal interconnects increases, but parasitic capacitance between interconnects increases leading to RC delay and cross-talk
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent conductive features and replaces it with air gaps. By removing the solid dielectric material that causes parasitic capacitance and inserting air (which has near-zero dielectric constant), the invention directly eliminates the source of RC delay and cross-talk while maintaining high integration density
Solution Approach 2:
The patent introduces porous air gap structures between conductive features instead of using solid dielectric materials. These air gaps act as porous regions with extremely low effective dielectric constant, reducing parasitic capacitance between adjacent interconnects while allowing the circuit layout to maintain high density
2Object-generated harmful factors
If air gaps are formed between conductive features to reduce parasitic capacitance, then coupling capacitance decreases, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming inhibitor caps on conductive features before depositing the dielectric material. These inhibitor caps are deposited in advance to define where air gaps should form, and then the dielectric material is selectively deposited only in regions not covered by the inhibitor caps, automatically creating the air gap pattern without requiring complex post-processing
Solution Approach 2:
The patent uses inhibitor caps as intermediary elements that mediate between the conductive features and the dielectric material. The inhibitor caps serve as temporary structures that control the deposition process, allowing selective formation of air gaps through their presence or absence, and are later removed after serving their purpose
3Loss of time
If inhibitor caps are selectively deposited on conductive features to form air caps, then air gaps are created to reduce RC delay, but the number of process steps increases
Solution Approach 1:
The patent merges the formation of air gaps with the existing dielectric deposition process. By integrating the inhibitor cap deposition and selective dielectric deposition into the standard interconnect fabrication flow, the air gap formation becomes a combined operation rather than a separate process, reducing the overall number of discrete process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces coupling capacitance by 5% or greater, enhancing device performance by minimizing RC delay and addressing reliability issues such as time-dependent dielectric breakdown and electromigration.
Implementation Method 1
selective deposition of inhibitor caps on the conductive features that are removed after a subsequent deposition of dielectric material
Implementation Method 2
The inhibitor caps may be removed via a plasma treatment
Implementation Method 3
Including air gaps between adjacent conductive features is beneficial to decrease coupling capacitance between the conductive features because the dielectric constant of air (e.g., around 1) is significantly less than the dielectric constant of solid low-k dielectric materials
Data Source
AI summary
A semiconductor device includes a first conductive feature, a first dielectric layer over the first conductive feature, a second conductive feature extending through the first dielectric layer, an air gap between the first dielectric layer and the second conductive feature, and an etch stop layer over the second conductive feature and the first dielectric layer. The etch stop layer covers the air gap, and the air gap extends above a bottommost surface of the etch stop layer.