Air-Gap BEOL Metallization for Low Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated chip elements scale, the reduced spacing between back-end-of-the-line (BEOL) metal interconnect features increases parasitic capacitance, leading to higher power consumption and larger RC time delays, which existing low-k dielectric materials struggle to mitigate due to processing issues such as peeling and package stress failure.
Innovation Solution
A method of forming a BEOL metallization layer with an air gap between adjacent metal interconnect features, using a sacrificial dielectric layer, a protective liner, and a re-distributed ILD layer to create a low dielectric constant environment, reducing capacitance and improving chip performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-k dielectric materials are used to reduce parasitic capacitance, then capacitance is reduced, but processing issues such as peeling and package stress failure occur
Solution Approach 1:
The patent extracts the problematic low-k dielectric material from the structure and replaces it with an air gap (vacuum/air region). This removes the harmful parasitic capacitance effect while avoiding the processing issues associated with low-k materials. The air gap is created by removing material rather than depositing problematic dielectric layers.
Solution Approach 2:
The patent introduces a porous structure in the form of an air gap within the inter-level dielectric layer. This porous region (air gap) provides extremely low dielectric constant (k≈1) to reduce parasitic capacitance, while being formed through material removal rather than deposition of problematic porous low-k materials that cause peeling and stress issues.
2Area of moving object
If spacing between metal interconnect features is reduced to scale integrated chip elements, then chip density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating air gaps specifically in the regions between adjacent metal interconnect features where parasitic capacitance is problematic. The air gap is not uniformly applied throughout the entire dielectric layer but is localized to specific high-capacitance regions, allowing reduced spacing between metals while maintaining low capacitance where it matters most.
Solution Approach 2:
The patent creates a composite inter-level dielectric structure consisting of a base dielectric material with localized air gap regions embedded within it. This composite structure combines the structural support properties of the solid dielectric with the low-capacitance properties of the air gap regions, enabling both reduced spacing and reduced parasitic capacitance.
3Object-affected harmful factors
If air gap is introduced to reduce parasitic capacitance, then capacitance and power consumption are reduced, but structural support may be compromised
Solution Approach 1:
The patent segments the inter-level dielectric layer by creating localized air gap regions rather than using a uniform structure. The air gaps are divided into discrete segments positioned between specific metal features, while the surrounding solid dielectric material provides structural support. This segmentation allows the low-capacitance benefit where needed while maintaining structural integrity through the distributed solid dielectric framework.
Solution Approach 2:
The solid dielectric material acts as an intermediary between the metal interconnect features, providing structural support while the air gaps provide electrical isolation. The intermediary dielectric layer bridges the structural and electrical requirements, supporting the metals mechanically while the air gaps reduce capacitive coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap within the ILD layer significantly reduces parasitic capacitance, enhancing integrated chip performance by lowering power consumption and RC time delays while maintaining structural integrity of the metal interconnect features.
Implementation Method 1
The air gap reduces the dielectric constant between the first and second features of the metal interconnect layer
Data Source
AI summary
The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.