Air-Gap Landing Pad Structure for Lower Bit Line Capacitance

Solution Overview

Problem

The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues related to parasitic capacitance and power consumption.

Innovation Solution

The introduction of an air gap between the landing pad and the bit line conductive layer in the semiconductor device design, which is formed by a method involving the deposition of a bit line conductive layer, a bit line inner capping layer, and a sealing layer, reduces parasitic capacitance and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the dimensions of semiconductor devices are scaled down, then computing ability is improved, but parasitic capacitance and power consumption increase

Engineering Contradiction:

Improvecomputing abilityVSAvoidpower consumption

Core Design Contradiction:

PowerVSLoss of energy

Solution Approach 1:

The patent extracts the harmful dielectric material between the bit line conductive layer and landing pad, replacing it with an air gap. This removal of the dielectric layer eliminates the source of parasitic capacitance while maintaining the electrical connection functionality, directly addressing the power consumption issue arising from device scaling.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the physical parameter of the insulating medium from a solid dielectric material to air (vacuum). This parameter change reduces the permittivity from typical dielectric values (3-10) to approximately 1 for air, thereby reducing parasitic capacitance and the associated power consumption in scaled-down devices.

Inventive Principle:

Principle #35Parameter changes

2Power

If the dimensions of semiconductor devices are scaled down, then computing ability is improved, but parasitic capacitance increases

Engineering Contradiction:

Improvecomputing abilityVSAvoidparasitic capacitance

Core Design Contradiction:

PowerVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the harmful dielectric material between the bit line conductive layer and landing pad, replacing it with an air gap. This removal of the dielectric layer eliminates the source of parasitic capacitance while maintaining the electrical connection functionality, directly addressing the power consumption issue arising from device scaling.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the physical parameter of the insulating medium from a solid dielectric material to air (vacuum). This parameter change reduces the permittivity from typical dielectric values (3-10) to approximately 1 for air, thereby reducing parasitic capacitance and the associated power consumption in scaled-down devices.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11985816B2Semiconductor device with air gap

Publication Date: 2024.05.14 NAN YA TECH

AI summary

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain region positioned in the substrate; a common source region positioned in the substrate and opposing to the drain region; a bit line structure including a bit line conductive layer positioned on the substrate and electrically coupled to the common source region; a cell contact positioned on the substrate, adjacent to the bit line structure, and electrically connected to the drain region; a landing pad positioned above the bit line conductive layer and electrically connected to the cell contact; and an air gap positioned between the landing pad and the bit line conductive layer.