Air-Gap Dielectric Between Vertical Capacitors

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Solution Overview

Problem

Integrated circuits with vertically oriented capacitors face challenges due to capacitive coupling, which cannot be effectively reduced by increasing distance between capacitors due to density limitations, and conventional low-k dielectric materials have limited capacity to decrease dielectric constants.

Innovation Solution

Incorporating air-gaps between capacitors to reduce capacitive coupling and forming additional capacitor conductors to increase capacitance, thereby doubling the capacitance provided by the capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the distance between capacitors is increased to decrease capacitive coupling, then coupling capacitance is reduced, but device density is limited

Engineering Contradiction:
Improvecapacitive couplingVSAvoiddevice density
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent introduces air-gaps specifically at the interfaces between adjacent vertically oriented capacitors, creating localized regions of low dielectric constant (k≈1) where capacitive coupling occurs. This targeted approach reduces coupling capacitance at critical interfaces without requiring increased spacing between capacitor structures, thereby maintaining high device density while eliminating harmful capacitive coupling effects.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If low-k dielectric materials are used to reduce dielectric constants, then capacitive coupling is reduced, but the capacity to reduce dielectric constants is limited

Engineering Contradiction:
Improvecapacitive couplingVSAvoiddielectric constant reduction capacity
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The patent fundamentally changes the dielectric constant parameter from typical low-k materials (k=2-4) to air-gaps with k≈1. This extreme parameter change achieves maximum possible dielectric constant reduction, thereby providing superior capacitive coupling reduction compared to conventional low-k dielectric materials while overcoming their limited reduction capacity.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If capacitor area is decreased to increase density, then device density is improved, but the amount of capacitance is limited

Engineering Contradiction:
Improvedevice densityVSAvoidcapacitance
Core Design Contradiction:
Area of stationary objectVSQuantity of substance

Solution Approach 1:

The patent converts the harmful effect of air-gaps (reduced capacitance due to low-k material) into a beneficial dual-plate capacitor structure. By positioning conductive plates on both sides of the air-gap, the structure simultaneously reduces capacitive coupling to adjacent capacitors while maintaining sufficient capacitance for memory operation, effectively converting a potential disadvantage into a functional advantage.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The air-gaps significantly reduce parasitic capacitance, stabilizing data storage and enabling high-speed operation with improved bandwidth, while the additional capacitor conductors provide sufficient capacitance for dense integrated circuit designs.

Implementation Method 1

Intracapacitor dielectric material and encapsulating dielectric structures with air-gaps for reducing parasitic capacitance

Methodology Applied
Scientific EffectDielectric effect: Dielectric

Data Source

PatentUS11574910B2Device with air-gaps to reduce coupling capacitance and process for forming such
Publication Date: 2023.02.07 INTEL CORP
  • US11574910B2 patent drawing
  • US11574910B2 patent drawing
  • US11574910B2 patent drawing

AI summary

A device is disclosed. The device includes a plurality of capacitors, a transistor connected to each of the plurality of capacitors, and a first dielectric layer and a second dielectric layer on respective adjacent sides of adjacent capacitors of the plurality of capacitors. The first dielectric layer and the second dielectric layer include a top portion and a bottom portion, the top portion of the first dielectric layer and the top portion of the second dielectric layer extend from respective directions and meet at a top portion of a space between the adjacent capacitors, the bottom portion of the first dielectric layer and the bottom portion of the second dielectric layer extend from respective directions and meet at a bottom portion of a space between the adjacent capacitors. The device also includes one or more air-gaps surrounded by the first dielectric layer and the second dielectric layer on respective adjacent sides of the adjacent capacitors, the top portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors, and the bottom portion of the first dielectric layer and the second dielectric layer between the adjacent capacitors.