3D Cross Rail Memory Air Gap Capacitive Coupling
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Solution Overview
Problem
Three-dimensional phase change memory devices face challenges in reducing capacitive coupling between conductive lines, leading to increased RC delay and performance limitations.
Innovation Solution
The implementation of a three-dimensional cross rail memory structure with air gaps, formed by creating a one-dimensional array of cavities between conductive rails, which reduces capacitive coupling by using sacrificial semiconductor structures and dielectric isolation layers to create encapsulated cavities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conductive rails are placed closer together to increase memory density, then storage capacity is improved, but capacitive coupling between rails increases causing increased RC delay
Solution Approach 1:
Air gaps are introduced as intermediary structures between adjacent conductive rails. These air gaps act as dielectric mediators that reduce capacitive coupling between rails while allowing the rails to remain in close proximity for high density. The air gap serves as a buffer zone that electrically isolates adjacent rails without requiring additional spacing that would reduce memory density.
Solution Approach 2:
The structure transitions from uniform spacing to non-uniform local spacing with air gaps strategically positioned between specific rails. This local quality approach allows different regions of the memory device to have different spacing characteristics - air gaps in critical coupling regions and minimal spacing in non-critical regions - optimizing both density and performance locally.
2Reliability
If air gaps are introduced to reduce capacitive coupling, then RC delay is reduced, but device fabrication complexity increases
Solution Approach 1:
Air gap structures are formed preliminarily during the fabrication process using sacrificial materials that are later removed. The air gaps are created as part of the rail formation process itself, before final device assembly, which simplifies subsequent processing steps and integrates the air gap formation into the existing fabrication workflow.
Solution Approach 2:
Sacrificial semiconductor structures are temporarily introduced during fabrication to define and form the air gap regions, then these sacrificial structures are completely removed (discarded) to create the final air gap structures. This approach allows complex air gap patterns to be formed using standard deposition and etching processes without requiring new fabrication equipment or techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitive coupling, thereby improving device performance by minimizing RC delay and enhancing the overall efficiency of the phase change memory device.
Implementation Method 1
The transition between the amorphous state and the crystalline state can be induced by controlling the rate of cooling after application of an electrical pulse that renders the phase change memory material in a first part of a programming process.
Implementation Method 2
If rapid quenching occurs, the phase change memory material can cool into an amorphous high resistivity state.
Implementation Method 3
If slow cooling occurs, the phase change memory material can cool into a crystalline low resistivity state.
Data Source
AI summary
A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, a rectangular array of first memory pillar structures, each containing a memory element, overlying top surfaces of the first conductive rails, second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures, and a one-dimensional array of first cavities free of solid material portions therein, laterally extending along the second horizontal direction and located between neighboring pairs of the second conductive rails.