3D Memory Air Gap Drain Select Gate Isolation
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Solution Overview
Problem
As the size of drain select transistors in three-dimensional memory devices shrinks, the width of drain-select-level isolation structures decreases, leading to increased dielectric breakdown and capacitive coupling between neighboring drain select gate electrodes, which affects the reliability and performance of the memory devices.
Innovation Solution
Incorporating air gaps, also referred to as cavity isolation, between adjacent drain select gate electrodes in the dielectric cap layer to reduce dielectric breakdown and capacitive coupling, which is achieved through a specific method of forming alternating stacks of insulating and spacer material layers, creating memory stack structures with vertical semiconductor channels and forming drain-select-level pillar structures with air gaps between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of drain-select-level isolation structures is decreased to accommodate shrinking transistor sizes, then device density is improved, but dielectric breakdown and capacitive coupling between neighboring drain select gate electrodes increase
Solution Approach 1:
The patent extracts the problematic dielectric material from between the drain select gate electrodes and replaces it with air gaps. This is achieved by forming voids or cavities in the isolation structures, effectively removing the dielectric material that causes breakdown and coupling issues while maintaining the structural integrity and electrical isolation function.
Solution Approach 2:
The patent introduces porous or hollow structures within the drain-select-level isolation structures. These porous features create air gaps that provide electrical isolation between neighboring gate electrodes, reducing capacitive coupling and preventing dielectric breakdown while allowing the isolation structures to maintain their mechanical support function.
2Productivity
If the width of drain-select-level isolation structures is decreased to accommodate shrinking transistor sizes, then device density is improved, but capacitive coupling between neighboring drain select gate electrodes increases
Solution Approach 1:
The patent extracts the problematic dielectric material from between the drain select gate electrodes and replaces it with air gaps. This is achieved by forming voids or cavities in the isolation structures, effectively removing the dielectric material that causes breakdown and coupling issues while maintaining the structural integrity and electrical isolation function.
Solution Approach 2:
The patent introduces porous or hollow structures within the drain-select-level isolation structures. These porous features create air gaps that provide electrical isolation between neighboring gate electrodes, reducing capacitive coupling and preventing dielectric breakdown while allowing the isolation structures to maintain their mechanical support function.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a substrate, memory stack structures extending through the alternating stack and containing a respective vertical semiconductor channel and a respective memory film, drain select gate electrodes located over the alternating stack, extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction, and a dielectric cap layer located between adjacent drain select gate electrodes. An air gap is located between adjacent drain select gate electrodes in the dielectric cap layer.