Air Gap Cavities Between Source/Drain Contacts in FETs
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Solution Overview
Problem
The miniaturization of field effect transistors (FETs) in integrated circuits has led to increased parasitic capacitance due to dielectric materials, which reduces operating speed and packing density, necessitating a method to reduce parasitic capacitance between source/drain contacts and gate electrodes.
Innovation Solution
Forming air gaps between source/drain contacts using a dielectric material that defines an air gap cavity, thereby reducing parasitic capacitance and enhancing operating speed and packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric materials are used to separate source/drain contacts, then electrical insulation is provided, but parasitic capacitance increases reducing operating speed
Solution Approach 1:
The patent changes the dielectric parameter by using air (vacuum) instead of traditional dielectric materials in the air gap region between source/drain contacts. This parameter change reduces the dielectric constant from typical values (3.9 for SiO2) to approximately 1.0 for air, thereby minimizing parasitic capacitance while maintaining electrical insulation functionality.
Solution Approach 2:
The patent applies different dielectric properties to different regions: traditional dielectric materials are used in regions requiring robust insulation, while air gaps are introduced in regions where parasitic capacitance must be minimized. This local differentiation optimizes both insulation and speed performance in their respective locations.
2Productivity
If FET dimensions are reduced to increase packing density, then more transistors fit per unit area, but parasitic capacitance effects become more significant
Solution Approach 1:
By changing the dielectric parameter to air in the air gap regions, the patent reduces parasitic capacitance effects that become increasingly significant as FET dimensions are scaled down. This allows continued miniaturization while maintaining acceptable parasitic capacitance levels.
Solution Approach 2:
The patent introduces a vertical dimension solution by creating air gap cavities between source/drain contacts. This vertical separation using air gaps addresses the parasitic capacitance issue without requiring further lateral scaling, enabling continued density improvement while controlling parasitic effects.
3Speed
If air gaps are formed between source/drain contacts, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial layers and defining air gap cavities during earlier process stages before final contact formation. This preliminary structuring simplifies subsequent steps and integrates air gap formation into the existing manufacturing flow rather than adding separate complex processes.
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures that temporarily occupy the air gap space during manufacturing. These intermediaries are later removed to create the final air gaps, providing a controlled and manufacturable approach to forming the desired structure.
Data Source
AI summary
One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.