Air-Gap Fill Structure for Low-Capacitance FinFET Isolation
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Solution Overview
Problem
The scaling down of semiconductor devices has increased complexity and resulted in undesirable parasitic capacitances due to the high dielectric constant of silicon nitride fill structures, which adversely impact device performance by increasing RC time delay.
Innovation Solution
Incorporating an air gap with a dielectric constant of about 1 in the fill structure, formed by depositing a SiN-based dielectric material at a first rate to create the air gap and a second rate to seal it, reducing the overall dielectric constant and preventing damage during subsequent processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride fill structures are used, then device isolation is achieved, but parasitic capacitance increases due to high dielectric constant
Solution Approach 1:
The patent introduces air gaps (porous structures) within the fill structure to reduce the overall dielectric constant. By creating a composite fill structure with regions of air (dielectric constant ≈1) and silicon nitride, the effective dielectric constant is reduced from approximately 7-8 to lower values, thereby reducing parasitic capacitance while maintaining device isolation functionality
Solution Approach 2:
The patent creates a composite fill structure combining silicon nitride with air gaps. This composite approach allows the fill structure to maintain mechanical strength and isolation properties from the silicon nitride while reducing parasitic capacitance through the air regions with low dielectric constant, achieving a balance between isolation performance and capacitance reduction
2Object-generated harmful factors
If air gap is incorporated in fill structure, then parasitic capacitance is reduced, but structural integrity may be compromised
Solution Approach 1:
The patent applies local quality by positioning air gaps specifically in certain regions of the fill structure rather than uniformly throughout. The air gaps are strategically placed to reduce parasitic capacitance in critical areas while maintaining sufficient structural integrity in other regions, achieving localized optimization without compromising overall strength
3Shape
If deposition rate is varied to form air gap, then air gap structure is created, but process complexity increases
Solution Approach 1:
The patent employs dynamic control of the deposition process by varying the deposition rate during film formation. The deposition rate is adjusted in real-time to create the desired air gap structure within the fill structure, transforming a static deposition process into a dynamic one that can create complex internal geometries through controlled parameter changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The air gap reduces parasitic capacitance by 20% to 50% compared to fill structures with only SiN-based dielectric materials, improving device performance while preventing etch back and damage during chemical mechanical planarization and etch processes.
Implementation Method 1
formed by depositing a SiN-based dielectric material at a first rate to create the air gap and a second rate to seal it
Data Source
AI summary
The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.