Air-Gap FinFET Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to scale down in size, the development of three-dimensional multi-gate structures like FinFETs is necessary to replace planar CMOS devices, requiring advanced manufacturing processes to achieve precise control over the semiconductor fins and gate structures for improved electrical performance.
Innovation Solution
The manufacturing process involves forming semiconductor fins on a substrate, depositing insulating materials, creating dummy gate stacks, growing strained materials for stress induction, and replacing these with gate stacks while forming air gaps to reduce parasitic capacitance and enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor devices are scaled down in size, then device density and integration are improved, but manufacturing precision and control over fin structures become more difficult to achieve
Solution Approach 1:
The manufacturing process is divided into multiple sequential steps including forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation allows precise control over fin dimensions and spacing by independently controlling each deposition and removal step, achieving the required manufacturing precision for scaled-down devices
Solution Approach 2:
Dummy gate stacks are formed preliminary before the actual gate structures. These dummy gates serve as placeholders that define the final gate position and dimensions. By establishing the gate layout in advance, the process ensures precise fin structure control and dimensional consistency across the device array, addressing the manufacturing precision challenge in scaled-down devices
2Area of moving object
If device size is reduced, then device density is improved, but parasitic capacitance between adjacent structures increases
Solution Approach 1:
Air gaps are introduced by removing dielectric material between adjacent fin structures and gate stacks. This extraction of material creates void spaces that eliminate parasitic capacitance coupling between neighboring devices. The air gaps are strategically positioned in regions where capacitive coupling would otherwise occur, directly addressing the harmful parasitic capacitance effect while maintaining compact device dimensions
Solution Approach 2:
The air gap structure provides different dielectric properties in different regions: air (low permittivity) between adjacent fins to reduce capacitance, and solid dielectric material in other regions for mechanical support and electrical isolation. This local differentiation of material properties allows simultaneous reduction of parasitic capacitance and maintenance of device structural integrity at scaled dimensions
3Reliability
If three-dimensional multi-gate structures are developed, then electrical control over channel is improved, but device complexity increases
Solution Approach 1:
The invention transitions from planar two-dimensional transistor structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This addition of the vertical dimension enables the gate to wrap around the channel on multiple sides, providing superior electrostatic control and drive current. The multi-gate configuration achieved through this dimensional transition improves electrical control while the self-aligned fabrication process manages the associated structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables improved electrical control and reduced parasitic capacitance, leading to enhanced performance and reliability of FinFETs by optimizing the structure and materials used in the fabrication of FinFETs.
Implementation Method 1
growing strained materials for stress induction
Implementation Method 2
forming air gaps to reduce parasitic capacitance
Data Source
AI summary
A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.