Air Gap Inner Spacers for Gate-All-Around Semiconductor Devices
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Solution Overview
Problem
Current methods for fabricating gate-all-around (GAA) devices face challenges with device fabrication and performance, particularly in forming Si or SiGe nanowire/nano sheet structures, air gaps as inner spacers, and metal gate structures, including defects and voids in the source/drain epitaxial layer.
Innovation Solution
A process flow and device structure are provided that include air gaps as inner spacer elements for GAA devices, allowing for improved isolation and a more conducive environment for source/drain formation, using a method that forms air gaps between nanowire or nanosheet channel regions and gate stacks, which reduces parasitic capacitance and enhances device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used for GAA devices, then manufacturing process can be established, but defects and voids appear in source/drain epitaxial layer
Solution Approach 1:
The patent removes the problematic inner spacer material (such as silicon oxide or silicon nitride) from between the nanowire channel regions, replacing it with air gaps. This extraction of the inner spacer eliminates the source of defects and voids that occur during conventional epitaxial growth, allowing for high-quality source/drain layer formation without contamination or interference from the spacer material.
Solution Approach 2:
The patent changes the physical state and material composition of the inner spacer region from solid material (oxide or nitride) to air gaps. This parameter change fundamentally alters the epitaxial growth environment, eliminating the harmful effects of spacer material on source/drain layer quality while maintaining the necessary structural support and electrical isolation functions.
2Speed
If inner spacers are used in GAA devices, then structural support is provided, but parasitic capacitance increases and device speed decreases
Solution Approach 1:
The patent employs air gaps (gaseous medium) instead of solid dielectric materials as inner spacers. This pneumatic approach replaces solid oxide or nitride spacers with air-filled spaces, which have significantly lower dielectric constants. The air gaps provide electrical isolation while minimizing parasitic capacitance between adjacent nanowire channels, thereby enhancing device switching speed and reducing signal delay.
Solution Approach 2:
The patent changes the dielectric constant parameter of the inner spacer region from high values (oxide: ~3.9, nitride: ~7.5) to air (~1.0). This parameter change directly reduces parasitic capacitance by more than 70% compared to conventional oxide spacers, enabling faster device operation while maintaining structural integrity through alternative support mechanisms.
3Reliability
If complex fabrication processes are used for GAA devices, then device performance can be optimized, but manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the inner spacer formation step from the fabrication process entirely. By removing the deposition and patterning of inner spacer materials (silicon oxide or silicon nitride), the process flow is simplified while simultaneously improving device performance. The air gap formation is achieved through selective removal of sacrificial materials or direct self-aligned processes, reducing the total number of manufacturing steps.
Solution Approach 2:
The air gap structure serves multiple functions simultaneously: it provides electrical isolation between adjacent nanowire channels, reduces parasitic capacitance, and eliminates the need for separate inner spacer materials. This multi-functionality consolidates several required features into a single structural element, simplifying the overall fabrication process while maintaining or enhancing device performance.
Data Source
AI summary
Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers.