Air Gap Between Gate-All-Around Transistors
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Solution Overview
Problem
The complexity of manufacturing semiconductor devices leads to issues such as poor electrical interconnection due to misalignment between upper and lower conductive features, necessitating improvements in the manufacturing process to enhance integration and reduce parasitic capacitance.
Innovation Solution
The semiconductor device incorporates a landing pad structure with an air gap below it, formed between lower plugs or gate stacks, which increases the landing area for upper plugs and reduces parasitic capacitance by using a dielectric layer to enclose the air gap, thereby improving alignment and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the manufacturing process integrates more conductive features in smaller size, then the functionality and integration of semiconductor devices are improved, but the alignment between upper and lower conductive features deteriorates leading to poor electrical interconnection
Solution Approach 1:
The patent introduces a lateral dimension solution by forming the landing pad structure that extends outward from the lower conductive feature. This lateral extension provides a larger target area for upper conductive features to align with, effectively solving the alignment problem in the planar dimension without requiring changes to the vertical stacking approach.
Solution Approach 2:
The conductive connection is segmented into multiple components: lower conductive feature, landing pad structure, and upper conductive feature. This segmentation allows each component to be optimized independently - the lower feature maintains its original dimensions, while the landing pad provides an intermediate alignment buffer that improves connection reliability.
2Device complexity
If conventional manufacturing processes are used without air gaps, then the device structure is simpler, but parasitic capacitance increases reducing device performance
Solution Approach 1:
The patent extracts the dielectric material from between adjacent lower conductive features by forming air gaps. This removal of dielectric material eliminates the source of parasitic capacitance while the landing pad structure ensures that electrical connections are maintained through the air gap regions.
Solution Approach 2:
The patent introduces air gaps which create a porous or void structure between conductive features. This porous approach uses air (a material with near-zero dielectric constant) to replace solid dielectric material, thereby minimizing parasitic capacitance while maintaining structural integrity through the landing pad design.
3Manufacturing precision
If the landing area for upper plugs is increased to improve alignment, then misalignment is prevented, but the device area increases
Solution Approach 1:
The landing pad structure applies local quality by concentrating the area expansion only where needed - at the interface between upper and lower conductive features. The air gaps are localized between adjacent lower features, while the landing pads are localized at connection points. This localized approach improves alignment without proportionally increasing the overall device area.
Data Source
AI summary
The present disclosure provides a semiconductor device with an air gap between gate-all-around (GAA) transistors and a method for forming the semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed over a semiconductor substrate. At least one of the first gate stack and the second gate stack includes a plurality of gate layers, and the first gate stack and the second gate stack have an air gap therebetween. The semiconductor device also includes a first gate structure and a second gate structure disposed over the first gate stack and the second gate stack, respectively, and a first dielectric layer surrounds lower sidewalls of the first gate structure and lower sidewalls of the second gate structure. A width of the first gate structure is greater than a width of the first plug.