Air Gap Gate Structure for Reducing Capacitive Coupling
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in reducing capacitive coupling between the gate and source/drain due to high permittivity materials, which affects operating speed and accuracy.
Innovation Solution
The method involves forming a gate spacer using a material with low permittivity and creating an air gap between the gate and source/drain, achieved by forming a dummy gate pattern, spacers, and subsequently removing them to expose the substrate for the deposition of a high-k insulating film and metal gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional gate structures are used, then manufacturing is simpler, but capacitive coupling between gate and source/drain increases
Solution Approach 1:
The patent removes the traditional continuous gate structure and extracts only the necessary gating function, replacing it with discrete metal gate electrodes positioned over source and drain regions. This extraction eliminates the capacitive coupling pathway that existed in conventional continuous gate structures, directly resolving the harmful capacitive coupling while maintaining essential transistor functionality.
Solution Approach 2:
The patent introduces a gate insulating film as an intermediary layer between the metal gate electrodes and the channel region. This intermediary provides electrical isolation and controls the capacitive coupling characteristics, allowing the metal gate electrodes to function without direct capacitive coupling to the channel, thus resolving the contradiction between simplified structure and reduced capacitive coupling.
2Object-affected harmful factors
If high permittivity materials are used in gate structure, then capacitive coupling increases, but manufacturing is easier
Solution Approach 1:
The patent changes the dielectric parameter (permittivity) of the gate structure by using a gate insulating film with controlled permittivity characteristics. Instead of relying on high permittivity materials that increase capacitive coupling, the invention selects insulating materials with appropriate permittivity values that reduce unwanted capacitive effects while maintaining effective gate control, thus resolving the contradiction between material ease of manufacture and capacitive coupling reduction.
3Object-affected harmful factors
If dummy gate pattern and air gap structure are formed, then capacitive coupling is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The patent incorporates the formation of air gaps and metal gate electrodes as preliminary actions during the gate structure fabrication process. By planning and executing these steps early in the manufacturing sequence, the complex structures are integrated into the overall fabrication flow rather than being added as separate post-processing steps, thus reducing the impact on overall productivity while achieving capacitive coupling reduction.
Solution Approach 2:
The patent merges the formation of air gaps with the existing gate structure fabrication processes by integrating metal gate electrode deposition and air gap creation into the standard manufacturing sequence. This combining of operations allows the complex air gap structure to be formed using established fabrication techniques and process integration, minimizing the increase in manufacturing complexity while achieving the desired reduction in capacitive coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitive coupling, enhancing the operational characteristics of transistors by decreasing dielectric constant and improving performance.
Implementation Method 1
forming a gate spacer using a material having low permittivity
Implementation Method 2
reduces capacitive coupling between a gate and a source and/or a drain by forming a gate spacer using a material having low permittivity and an air gap
Data Source
AI summary
A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.