Air Gap Between Gate Electrode and Active Area

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Solution Overview

Problem

The row hammer phenomenon in dynamic random access memory (DRAM) causes data loss or interference in adjacent rows due to frequent activation, becoming more severe with increasing DRAM design density.

Innovation Solution

A semiconductor structure with a trench isolation region, active areas, and conductive gate electrodes, featuring an air gap between the second gate electrode and the semiconductor substrate, which is sealed by a dielectric cap layer to reduce parasitic capacitance and mitigate data interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM design density is increased, then storage capacity is improved, but row hammer phenomenon becomes more severe

Engineering Contradiction:
Improvestorage capacityVSAvoidrow hammer phenomenon
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

An air gap is introduced as an intermediary layer between the second gate electrode and the semiconductor substrate. This air gap acts as a mediator that reduces parasitic capacitance between the gate electrode and substrate, thereby mitigating the row hammer phenomenon while preserving high-density storage capacity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric constant parameter is changed by replacing the traditional solid dielectric material with an air gap (dielectric constant of air is approximately 1.0, much lower than solid dielectrics). This parameter change reduces parasitic capacitance and suppresses row hammer effects while maintaining the high-density DRAM structure

Inventive Principle:
Principle #35Parameter changes

2Productivity

If gate electrode is placed adjacent to distal end portion of active area, then device density is improved, but parasitic capacitance increases

Engineering Contradiction:
Improvedevice densityVSAvoidparasitic capacitance
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

An air gap is introduced as an intermediary layer between the second gate electrode and the semiconductor substrate. This air gap acts as a mediator that reduces parasitic capacitance between the gate electrode and substrate, thereby mitigating the row hammer phenomenon while preserving high-density storage capacity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric constant parameter is changed by replacing the traditional solid dielectric material with an air gap (dielectric constant of air is approximately 1.0, much lower than solid dielectrics). This parameter change reduces parasitic capacitance and suppresses row hammer effects while maintaining the high-density DRAM structure

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The air gap effectively reduces parasitic capacitance, thereby suppressing the row hammer phenomenon and improving data integrity in DRAM structures.

Implementation Method 1

The air gap effectively reduces parasitic capacitance, thereby suppressing the row hammer phenomenon and improving data integrity in DRAM structures

Methodology Applied
Scientific EffectParasitic capacitance reduction: Capacitance

Data Source

PatentUS10714481B2Semiconductor structure having air gap between gate electrode and distal end portion of active area and fabrication method thereof
Publication Date: 2020.07.14 UNITED MICROELECTRONICS CORP
  • US10714481B2 patent drawing
  • US10714481B2 patent drawing
  • US10714481B2 patent drawing

AI summary

A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.