Air-Gap Gate Sidewall Spacer for Self-Aligned Contacts
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Solution Overview
Problem
Existing methods for forming integrated circuit structures with air-gap gate sidewall spacers are incompatible with forming gate contacts over active regions, leading to issues with parasitic capacitance and shorting risks.
Innovation Solution
A method involving the formation of a sacrificial gate sidewall spacer, selective etching to create a cavity, and deposition of a dielectric spacer layer that pinches off to form an air-gap gate sidewall spacer, allowing for self-aligned gate contacts over active regions without shorting risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional gate sidewall spacer is used, then the structure is simple to form, but parasitic capacitance between the gate and metal plugs is high
Solution Approach 1:
The patent removes the traditional solid dielectric material from the gate sidewall spacer region and replaces it with an air gap. This extraction of material creates a void space that eliminates the parasitic capacitance pathway between the gate and metal plugs, directly addressing the harmful electrical effect while maintaining the structural function of the spacer.
Solution Approach 2:
The patent introduces an air-gap gate sidewall spacer that creates a porous or void structure in the region between the gate and metal plugs. This air-filled space acts as an electrical insulator with minimal capacitance, reducing the parasitic effect while still providing the necessary physical separation and structural support.
2Reliability
If gate contacts are formed outside the active region, then shorts between gate contact and metal plugs are avoided, but the IC structure area increases
Solution Approach 1:
The air-gap gate sidewall spacer serves as an intermediary structure that enables the gate contact to be positioned over the active region without creating shorts to metal plugs. The air gap acts as an electrical barrier that prevents direct capacitive coupling or physical contact between the gate contact and adjacent metal plugs, allowing compact layout while maintaining electrical isolation.
3Stability of the object's composition
If an air-gap gate sidewall spacer is formed with complete cavity filling, then the spacer is continuous, but the air-gap is lost and parasitic capacitance increases
Solution Approach 1:
The gate sidewall spacer is segmented into two distinct portions: a lower portion containing the air gap for capacitance reduction, and an upper portion filled with dielectric material for structural continuity. This segmentation allows each portion to fulfill its specific function - the air-gap portion minimizes parasitic capacitance while the filled portion provides mechanical support and continuity.
Solution Approach 2:
The patent applies different material properties to different regions of the gate sidewall spacer. The lower portion adjacent to the gate and metal plugs contains an air gap for electrical isolation and low capacitance, while the upper portion is filled with dielectric material for structural stability. This local differentiation of material quality optimizes both electrical performance and mechanical integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces parasitic capacitance and enables the formation of gate contacts over active regions, minimizing the risk of shorts and allowing for size scaling in integrated circuit structures.
Implementation Method 1
a dielectric spacer layer can be deposited such that it pinches off before filling the cavity completely
Data Source
AI summary
A method is disclosed wherein a gate, having a gate cap and a sacrificial gate sidewall spacer, is formed adjacent to channel region(s) of a transistor and metal plugs, having plug caps, are formed on source/drain regions. The sacrificial gate sidewall spacer is selectively etched, creating a cavity that exposes sidewalls of the gate and gate cap. Optionally, the sidewalls of the gate cap are etched back to widen the upper portion of the cavity. A dielectric spacer layer is deposited to form an air-gap gate sidewall spacer within the cavity. Since different materials are used for the plug caps, gate cap and dielectric spacer layer, a subsequently formed gate contact opening will be self-aligned to the gate. Thus, a gate contact can be formed over an active region (or close thereto) without risk of gate contact-to-metal plug shorting. A structure formed according to the method is also disclosed.