Air-Gap Isolated On-Chip Inductors for Low-Loss Compact Layouts
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Solution Overview
Problem
The design of on-chip inductors in semiconductor devices faces a tradeoff between the size of the inductor and its quality factor, which affects energy loss and storage.
Innovation Solution
The structure includes a semiconductor substrate with sealed cavities containing air gaps and a back-end-of-line stack with an inductor winding that overlaps with the sealed cavities, optimizing the balance between inductor size and quality factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the inductor size is increased to improve quality factor, then energy loss is reduced, but the area occupied on the chip increases
Solution Approach 1:
The patent introduces sealed cavities extending vertically into the substrate beneath the inductor winding, utilizing the third dimension (depth) to provide electrical isolation. This allows the inductor to maintain a compact planar footprint while achieving low energy loss through vertical isolation structures, effectively resolving the tradeoff between inductor area and energy loss.
2Area of stationary object
If the inductor size is decreased to reduce chip area, then space is saved, but energy loss increases and quality factor decreases
Solution Approach 1:
By implementing sealed cavities that extend vertically into the substrate, the patent enables compact planar inductor designs to achieve low energy loss. The vertical isolation structures provide electrical isolation without requiring larger planar dimensions, allowing small-footprint inductors to maintain high quality factors.
Solution Approach 2:
The sealed cavities filled with air or dielectric material act as intermediary structures between the inductor winding and the conductive substrate. These intermediate layers prevent direct electrical coupling and reduce parasitic losses, enabling compact inductors to achieve low energy loss through the mediating isolation structures.
3Loss of energy
If sealed cavities are introduced to reduce energy loss, then quality factor improves, but device complexity increases
Solution Approach 1:
The substrate is segmented into multiple sealed cavities beneath the inductor winding, with each cavity providing localized electrical isolation. This segmentation approach distributes the isolation function across multiple discrete structures, making the complex isolation requirement manageable through repetitive modular units rather than a single complex structure.
Solution Approach 2:
The sealed cavities create a porous-like structure within the substrate, with voids filled with air or dielectric material providing electrical isolation. This porous architecture achieves effective isolation while maintaining a relatively simple fabrication process using standard etching and deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality factor of the inductor by reducing energy losses to the substrate while maintaining a compact footprint, thereby optimizing inductor performance.
Implementation Method 1
Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the sealed cavities
Data Source
AI summary
Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.