Air-Gap Inner Spacers for Low-Capacitance GAA Transistors
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Solution Overview
Problem
The challenge in fabricating gate-all-around (GAA) transistors is the increased complexity in reducing parasitic capacitance without shortening the effective channel length, as thicker inner spacers used to reduce capacitance can induce adverse short-channel effects.
Innovation Solution
The method involves forming inner spacers with an air gap embedded in a dielectric material, which are deposited in a high-pulse mode to create an overhung structure, maintaining sufficient channel length while reducing parasitic capacitance, and using a second spacer layer with a higher dielectric constant to prevent growth into the air gap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If thicker inner spacers are used to reduce parasitic capacitance, then parasitic capacitance is reduced, but effective channel length is shortened causing adverse short-channel effects
Solution Approach 1:
The inner spacer structure is made non-uniform by creating an air gap at a specific location within the spacer. This local modification allows the spacer to reduce parasitic capacitance where needed (near the gate) while maintaining sufficient length in other regions to prevent short-channel effects, thus achieving different functional requirements at different locations of the same component.
Solution Approach 2:
The inner spacer is constructed as a composite structure combining dielectric material and air gap. The dielectric portion provides the necessary spacing and capacitance reduction, while the air gap portion maintains the effective channel length without adding parasitic capacitance. This composite approach allows simultaneous optimization of both contradictory requirements.
2Object-affected harmful factors
If inner spacers are made thicker to reduce parasitic capacitance, then capacitance reduction is achieved, but device complexity increases
Solution Approach 1:
The air gap is formed during the inner spacer deposition process itself through high-pulse mode deposition that creates an overhung structure. This preliminary formation of the air gap eliminates the need for subsequent complex steps such as drilling, etching, or injecting air into the spacer, thereby reducing fabrication complexity while still achieving the desired capacitance reduction.
Solution Approach 2:
The deposition process automatically creates the air gap structure through the overhung morphology that forms during high-pulse mode deposition. The process self-organizes to produce the required air gap without external intervention or additional processing steps, simplifying the overall fabrication sequence while maintaining the capacitance reduction benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance in GAA transistors without shortening the channel length, improving device performance by maintaining gate control and mitigating short-channel effects.
Implementation Method 1
forming an inner spacer layer in the S/D recess, wherein forming the inner spacer layer includes recessing a portion of each non-channel layer to form a trench and depositing an inner spacer layer in the trench, thereby forming an air gap in the inner spacer layer
Implementation Method 2
providing inner spacers capable of reducing parasitic capacitance becomes more challenging when device sizes continue to decrease
Data Source
AI summary
A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap enclosed in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.