Air Gap Interconnect Structure for Low-k Dielectric RC Reduction

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Solution Overview

Problem

As semiconductor device sizes decrease, capacitive coupling between metal interconnect layers increases, limiting chip speed and proper operation, necessitating an improved method for forming an interconnect structure with reduced RC time constants.

Innovation Solution

The implementation of a gap-containing interconnect structure, where air gaps are introduced between the conductive features and dielectric layers, reducing the effective dielectric constant and thereby lowering the RC time constants, using a combination of low-k dielectric materials and etch stop layers to support the conductive features and facilitate gap formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of semiconductor devices decreases, then device density and integration increase, but capacitive coupling between metal interconnect layers increases

Engineering Contradiction:
Improvedevice densityVSAvoidcapacitive coupling
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent introduces air gaps as intermediary spaces between conductive features and dielectric layers. These air gaps act as mediators that reduce the effective dielectric constant of the insulating material, thereby reducing capacitive coupling between adjacent metal interconnect layers while allowing continued device scaling and high density integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs porous or gap-containing dielectric structures where air voids are intentionally created within the dielectric material. This porous structure reduces the effective dielectric constant (k-value) of the insulating layer, directly addressing the capacitive coupling issue that arises from device miniaturization and increased layer density.

Inventive Principle:
Principle #31Porous materials

2Speed

If air gaps are introduced to reduce capacitive coupling, then RC time constants decrease and chip speed improves, but manufacturing complexity increases

Engineering Contradiction:
Improvechip speedVSAvoidmanufacturing complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent incorporates etch stop layers and support structures during the fabrication process that are designed to facilitate subsequent air gap formation. These preliminary structures are built in advance to guide and support the creation of air gaps, making the complex manufacturing process more controllable and repeatable despite the increased complexity introduced by air gap technology.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly improves RC performance by reducing the effective dielectric constant, enhancing chip speed and operation, with air gaps providing a 15% reduction in dielectric constant for a 10% gap, and allowing for the use of materials with dielectric constants less than 3.9, such as organic polymers and silicon-based polymers.

Implementation Method 1

air gaps are introduced between the conductive features and dielectric layers, reducing the effective dielectric constant and thereby lowering the RC time constants

Methodology Applied
Scientific EffectDielectric constant reduction: Dielectric Permittivity

Data Source

PatentUS10985054B2Interconnect structure and method of forming the same
Publication Date: 2021.04.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10985054B2 patent drawing
  • US10985054B2 patent drawing
  • US10985054B2 patent drawing

AI summary

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.