Air-Gap Interconnect Fabrication for Reduced Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices integrate at higher levels, the gap between conductive layers shrinks, increasing parasitic capacitance and resulting in resistance-capacitance (RC) delay, which hinders signal transfer speed.
Innovation Solution
A manufacturing method for an interconnect structure that includes forming sacrificial layers, air gaps in dielectric layers, and conductive layers, with isotropic etching and chemical mechanical polishing processes to reduce parasitic capacitance by creating wider openings and using air gaps with lower dielectric constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gap between conductive layers is shrunk to increase integration degree, then the integration degree is improved, but the parasitic capacitance is increased
Solution Approach 1:
The patent introduces air gaps (porous structures) into the dielectric layer between conductive layers. These air gaps have lower dielectric constants compared to solid dielectric materials, thereby reducing parasitic capacitance while maintaining the physical structure needed for high integration degree.
Solution Approach 2:
The dielectric layer is constructed as a composite structure combining solid dielectric material and air gaps. This composite approach allows optimization of both mechanical support (provided by solid dielectric) and electrical performance (improved by low-k air gaps), resolving the contradiction between integration and parasitic capacitance.
2Productivity
If the gap between conductive layers is shrunk, then the integration degree is improved, but the resistance-capacitance delay is increased
Solution Approach 1:
Air gaps are introduced into the dielectric layer to reduce parasitic capacitance. Since RC delay is directly proportional to capacitance, reducing capacitance through air gaps effectively reduces the RC delay, allowing faster signal transfer despite smaller gaps between conductive layers.
3Object-generated harmful factors
If air gaps are formed in the dielectric layer, then the parasitic capacitance is reduced, but the manufacturing complexity is increased
Solution Approach 1:
Sacrificial layers are formed first in the dielectric layer before the final conductive layers are deposited. These sacrificial layers define the air gap locations and are subsequently removed, creating air gaps without requiring direct air gap formation processes. This preliminary structuring simplifies the overall manufacturing complexity.
Solution Approach 2:
Sacrificial layers act as intermediary structures that facilitate air gap formation. They are temporarily introduced to define air gap positions, then removed to create the desired air gap structure. This intermediary approach avoids the complexity of direct air gap creation while achieving the same result.
4Object-generated harmful factors
If isotropic etching is performed to increase the width of openings, then the parasitic capacitance is reduced, but the manufacturing precision is affected
Solution Approach 1:
The etching process parameters are optimized to achieve isotropic etching that uniformly widens openings. By controlling etch rate, temperature, and chemical composition, the process achieves sufficient opening width increase to reduce capacitance while maintaining acceptable dimensional control through parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces parasitic capacitance between conductive layers, thereby lowering resistance-capacitance delay and enhancing signal transfer speed.
Implementation Method 1
the air gaps have lower dielectric constants, the parasitic capacitance between conductive layers is reduced
Implementation Method 2
An isotropic etching process is performed on the sacrificial layers to increase a width of the second opening between two adjacent sacrificial layers
Implementation Method 3
The conductive material layer and the barrier material layer on an exterior of the first openings are removed to form the conductive layer and the barrier layer
Data Source
AI summary
A manufacturing method of an interconnect structure including the following is provided. A substrate is provided. Sacrificial layers are formed on the substrate. A dielectric layer is formed between two adjacent sacrificial layers. There is an air gap in the dielectric layer. The sacrificial layers are removed to form first openings. A conductive layer is formed in the first opening.