Air-Gap Interconnect Structure for Lower RC Delay in Dense Layouts
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Solution Overview
Problem
The integration of semiconductor structures faces challenges due to increased parasitic capacitance and RC delay in pattern-dense regions, leading to higher power consumption and signal delay, which complicates manufacturing and integration processes.
Innovation Solution
A semiconductor structure is designed with a first conductive layer, a dielectric layer, conductive plugs, spacers, and air gaps to reduce capacitive coupling, featuring a lining layer with manganese and second conductive plugs, and a method involving the formation of air gaps between spacers to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor structures are miniaturized and integrated with greater functionality, then device functionality and integration density are improved, but parasitic capacitance between adjacent conductive elements increases
Solution Approach 1:
The patent divides the continuous dielectric medium into segmented regions by introducing air gaps between adjacent conductive elements. This segmentation reduces the capacitive coupling area between neighboring conductors, thereby reducing parasitic capacitance while maintaining the integrated circuit's functional density and versatility.
Solution Approach 2:
The patent applies different dielectric properties locally by replacing the continuous dielectric material with air gaps in specific regions between conductive elements. This local modification of dielectric quality (from high-k dielectric to air with k≈1) reduces parasitic capacitance in critical areas while preserving the overall device functionality and integration density.
2Adaptability or versatility
If manufacturing operations are increased for integration of various semiconductor structures, then integration capability is improved, but manufacturing complexity increases
Solution Approach 1:
The air gaps are formed preliminarily during the dielectric layer formation process itself, rather than requiring separate post-processing steps. The dielectric layer is deposited conformally over the conductive elements, and air gaps are naturally created in predetermined regions, integrating the air gap formation into the existing manufacturing flow without adding significant process complexity.
Solution Approach 2:
The patent uses a sacrificial material or conformal dielectric deposition as an intermediary mechanism to create air gaps. The dielectric layer is deposited conformally, and through selective removal or void formation during deposition, air gaps are created as an intermediary structure that reduces parasitic capacitance without requiring complex additional manufacturing steps.
3Loss of energy
If air gaps are introduced to reduce parasitic capacitance, then power consumption and signal delay are reduced, but device structure complexity increases
Solution Approach 1:
The patent merges the air gap formation process with the existing dielectric layer deposition process. By depositing dielectric material conformally over conductive elements and allowing natural void formation or using sacrificial material removal, the air gaps are created as an integrated part of the standard manufacturing process rather than as a separate structural addition, thus reducing the net increase in device complexity.
Data Source
AI summary
The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.