Air-Gap Interconnect Structure Without Barrier RC Penalty
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Solution Overview
Problem
The formation of high-quality interconnects in semiconductor devices is challenging due to increased parasitic resistance and capacitance from diffusion barrier layers, which also require costly chemical mechanical polishing (CMP) processes.
Innovation Solution
A barrier-free interconnect layer is formed by selectively depositing a barrier layer on sidewalls of trenches using self-assembled monolayers or polymers, followed by rapid atomic layer deposition (ALD) of an inter-metal dielectric layer, eliminating the need for CMP and creating air gaps to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diffusion barrier layers are used in metallization, then metal diffusion is prevented, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent extracts and removes the diffusion barrier layer from the interconnect structure after metallization is complete. This eliminates the source of parasitic resistance and capacitance while the metal diffusion prevention function has already been served during the critical metallization phase.
Solution Approach 2:
The diffusion barrier layer is deposited before metallization to prevent metal diffusion during the high-temperature processing stages. Once metallization is complete, the barrier layer is removed since its protective function is no longer needed, thereby eliminating its harmful parasitic effects.
2Manufacturing precision
If CMP process is used for IMD layer deposition, then planarity is achieved, but processing cost and time increase
Solution Approach 1:
The patent removes the CMP process from the manufacturing sequence by using an alternative approach: depositing the IMD layer over the metal surface without requiring mechanical polishing, thereby eliminating this costly and time-consuming step while maintaining acceptable planarity through deposition control.
Solution Approach 2:
The mechanical CMP process is replaced with a deposition-based approach where the IMD layer is deposited directly onto the metal surface. This substitutes mechanical removal of material with a controlled deposition process, eliminating the need for CMP equipment and operations.
3Reliability
If barrier layer remains after metallization, then metal diffusion is prevented, but parasitic capacitance increases due to high dielectric constant
Solution Approach 1:
The patent extracts and removes the barrier layer after metallization is complete. The barrier layer serves its purpose during metallization to prevent metal diffusion, but is then removed to eliminate the parasitic capacitance caused by its high dielectric constant surrounding the metal lines.
Solution Approach 2:
The barrier layer is deposited in advance before metallization to prevent metal diffusion during high-temperature processing. After metallization completes, the barrier layer is removed since its protective function is no longer needed, thereby eliminating its harmful parasitic capacitance effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces parasitic capacitance and RC delay, increases processing throughput, and eliminates the need for costly CMP processes, while maintaining interconnect quality.
Implementation Method 1
selectively depositing a barrier layer on sidewalls of trenches using self-assembled monolayers or polymers
Implementation Method 2
rapid atomic layer deposition (ALD) of an inter-metal dielectric layer
Data Source
AI summary
A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.