Air Gap Interconnects for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor device sizes decrease, the reduced distance between interconnect lines leads to increased parasitic capacitance, affecting integrated circuit performance, and existing methods struggle to reduce this capacitance without damaging the device.
Innovation Solution
The formation of an air gap between interconnect lines using a substrate with a first dielectric layer, trench metal layers, a liner layer, and an etching stop layer to create a high-K dielectric seal, reducing parasitic capacitance without damaging the trench metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the distance between interconnect lines is reduced to decrease device area, then the area occupied by the semiconductor device is reduced, but the parasitic capacitance between interconnect lines increases
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent trench metal layers and replaces it with an air gap. By removing the solid dielectric material that causes parasitic capacitance and filling the space with air (or vacuum), the parasitic capacitance is significantly reduced while maintaining the reduced device area.
Solution Approach 2:
The patent changes the dielectric constant parameter of the material between interconnect lines from a high value (solid dielectric) to a low value (air/vacuum with dielectric constant ≈1). This parameter change directly reduces the parasitic capacitance between adjacent interconnect lines while allowing them to remain closely spaced.
2Object-generated harmful factors
If an air gap is formed between trench metal layers to reduce parasitic capacitance, then the parasitic capacitance effect is reduced, but the trench metal layers may be damaged during the etching process
Solution Approach 1:
The patent applies preliminary protective actions by forming a liner layer conformally over the trench metal layers and air gap profile, and then forming an etching stop layer over the liner layer before performing the etching process. These preliminary protective layers prevent direct contact between the etching chemistry and the trench metal layers, avoiding damage while allowing the air gap to be formed.
Solution Approach 2:
The patent introduces intermediary protective layers (liner layer and etching stop layer) that act as mediators between the etching process and the trench metal layers. These intermediary layers protect the metal layers from etching damage while still allowing the air gap to be formed in the dielectric material above them.
3Reliability
If a liner layer and etching stop layer are added to protect trench metal layers, then the trench metal layers are protected from damage, but the device complexity increases
Solution Approach 1:
The liner layer serves multiple functions: it protects the trench metal layers from etching damage, provides a conformal coating over the air gap profile, and serves as a base for the etching stop layer. The etching stop layer provides both protection during etching and acts as a stopping layer for subsequent etching processes. This multi-functionality reduces the need for additional separate protective layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance while minimizing damage to the interconnect lines, improving the performance of integrated circuits by creating a controlled air gap with a low-K dielectric material and high-K etching stop layer.
Implementation Method 1
a parasitic capacitance effect would occur between the interconnect lines and could influence the performance of the integrated circuit
Implementation Method 2
the first dielectric layer is a low-K dielectric material
Implementation Method 3
An etching stop layer is disposed on the liner layer, wherein the etching stop layer seals the air trench to form an air gap between the adjacent two of the trench metal layers
Data Source
AI summary
A structure of semiconductor device includes a substrate. A first dielectric layer is disposed over the substrate, wherein the first dielectric layer has an air trench. A plurality of trench metal layers is disposed in the first dielectric layer, wherein the air trench is between adjacent two of the trench metal layers and without contacting to the trench metal layers. A liner layer is disposed on the first dielectric layer to cover the trench metal layers and a profile of the air trench. An etching stop layer is disposed on the liner layer, wherein the etching stop layer seals the air trench to form an air gap between the adjacent two of the trench metal layers.