Air Gap Interconnects via Insulating Layer
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Solution Overview
Problem
In semiconductor devices, positional deviations between interconnects and vias can lead to the formation of voids due to the connection between air gaps and connection holes, resulting in increased capacitance and signal delay.
Innovation Solution
A semiconductor device structure featuring a first insulating layer with interconnects and air gaps, a second insulating layer between the air gaps and the first insulating layer, an etching stopper film, and a third insulating layer with vias connected to the interconnects, where the second insulating layer acts as an etching stopper to prevent connection between air gaps and vias even with positional deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an air gap is provided between the interconnect and the insulating film to reduce capacitance, then capacitance between interconnects is reduced, but positional deviation between vias and interconnects causes the air gap to connect with connection holes, forming voids that compromise device integrity
Solution Approach 1:
A second insulating layer is introduced as an intermediary between the first insulating layer (containing the air gap) and the etching stopper film. This intermediate layer acts as a buffer that prevents direct connection between the air gap and the etching stopper film, thereby eliminating the void formation problem while preserving the low-capacitance benefit of the air gap structure.
Solution Approach 2:
The insulating structure is segmented into multiple distinct layers: a first insulating layer containing the air gap, a second insulating layer positioned between the air gap and etching stopper film, and an etching stopper film. This segmentation allows each layer to fulfill its specific function independently, preventing the harmful interaction between air gaps and etching stopper film that occurs in monolithic structures.
2Area of stationary object
If the gap between interconnects is reduced to increase integration density, then device size is reduced, but capacitance between interconnects increases causing signal delay
Solution Approach 1:
The air gap is strategically positioned only in specific regions between the interconnect and the first insulating layer, creating a local low-dielectric constant region. This localized modification reduces capacitance precisely where needed between closely-spaced interconnects without requiring overall device expansion, thus maintaining high integration density while reducing signal delay.
3Manufacturing precision
If a diffusion barrier metal film and seed film are formed in the via and interconnect groove, then proper plating is achieved, but these films are not formed in and around the opening region connected to the air gap, resulting in void formation
Solution Approach 1:
The second insulating layer serves as an intermediary barrier that prevents the opening region connected to the air gap from being exposed during film formation. By positioning this intermediate layer between the air gap and the etching stopper film, the structure ensures that diffusion barrier metal films and seed films are deposited only in the intended via and interconnect groove regions, eliminating void formation while maintaining precise film placement.
Data Source
AI summary
An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. A second insulating layer is formed at least over the first insulating layer and the air gap. The second insulating layer does not cover the interconnect. An etching stopper film is formed at least over the second insulating layer. The etching stopper film is formed over the second insulating layer and the interconnect. A third insulating layer is formed over the etching stopper film. A via is provided in the third insulating layer so as to be connected to the interconnect.