Air Gap Interconnects for RF Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional methods for forming metal interconnect structures fail to effectively minimize parasitic capacitance between adjacent metal interconnects, especially at technology nodes below 32 nm, where low-K dielectric materials do not adequately reduce parasitic capacitance, and the conventional method of filling grooves with an intermetallic dielectric layer is insufficient for radio frequency integrated circuits.
Innovation Solution
A method involving the formation of grooves with a depth-to-width ratio greater than 0.8 between metal interconnects, followed by the deposition of an intermetallic dielectric layer that includes air gaps, which reduces the dielectric constant and parasitic capacitance between adjacent interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-K dielectric materials are used to form interlayer dielectric layer and intermetallic dielectric layer, then parasitic capacitance between adjacent metal interconnects is reduced, but at technology node below 32 nm, low-K dielectric materials cannot adequately reduce parasitic capacitance
Solution Approach 1:
The patent introduces air gaps (porous structures) within the intermetallic dielectric layer to reduce parasitic capacitance. The air gaps create void spaces that lower the effective dielectric constant of the intermetallic dielectric layer, providing superior capacitance reduction compared to solid low-K dielectric materials at advanced technology nodes below 32 nm.
Solution Approach 2:
The patent creates a composite intermetallic dielectric layer structure combining solid dielectric material with air gap voids. This composite structure achieves lower effective dielectric constant than conventional solid low-K materials, resolving the inadequacy of low-K materials at advanced technology nodes while maintaining reliability.
2Ease of manufacture
If conventional method fills groove with intermetallic dielectric layer, then groove is completely filled, but parasitic capacitance between two adjacent metal interconnects cannot be minimized
Solution Approach 1:
The patent deliberately creates air gaps (porous structures) within the filled groove structure. The intermetallic dielectric layer is deposited to cover the groove while intentionally leaving void spaces, creating a porous composite structure that reduces parasitic capacitance while maintaining complete groove coverage for manufacturing ease.
Solution Approach 2:
The patent applies local quality by creating non-uniform distribution of dielectric material within the groove. Air gaps are strategically positioned within the intermetallic dielectric layer at locations where parasitic capacitance reduction is most critical, while maintaining complete groove filling overall for manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased size of air gaps in the intermetallic dielectric layer reduces parasitic capacitance, leading to improved performance and reduced RC delay and power consumption in semiconductor devices, particularly in radio frequency integrated circuits.
Implementation Method 1
parasitic capacitance generated therebetween becomes greater... reduce parasitic capacitance between adjacent metal interconnects
Data Source
AI summary
An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming a conductive layer on the semiconductor substrate; forming a mask layer on the conductive layer; forming a groove in the mask layer and the conductive layer, the groove having a depth-to-width ratio greater than 0.8; and depositing an intermetallic dielectric layer to cover the mask layer and fill the groove, wherein an air gap is formed in a portion of the intermetallic dielectric layer in the groove. The mask layer is formed on the conductive layer, so that the depth-to-width ratio of the groove between adjacent interconnects is increased. Besides, the air gap with a relatively large size is formed between two adjacent interconnects. Therefore, a dielectric constant and parasitic capacitance between adjacent interconnects are reduced evidently, and the performance of the semiconductor devices is improved.