Air Gap Formation in Semiconductor Interconnects via Selective Etching
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Solution Overview
Problem
In stacked type semiconductor memory devices, the formation of air gaps between interconnects and vias is challenging due to misalignment and etching process errors, leading to reduced operational speed and stability.
Innovation Solution
A method involving the deposition of insulating films with different etching speeds to create and maintain air gaps between interconnects and vias, ensuring the lower end of the air gap is below the interconnect and upper end is above, thereby reducing capacitance and ensuring electrical separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form air gaps between interconnects and vias, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to misalignment and etching process errors
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the interconnect layer, which pre-defines the air gap position and dimensions. This mandrel serves as a template that guides subsequent etching processes, ensuring precise air gap formation without requiring complex real-time alignment during etching operations.
Solution Approach 2:
The mandrel acts as an intermediary element between the interconnect and via structures. It mediates the spatial relationship between these components, using its predetermined geometry to transfer precise positioning information to the final air gap formation, thereby eliminating direct alignment requirements between interconnect and via.
2Speed
If air gaps are not properly maintained between interconnects and vias, then device complexity is reduced, but operational speed deteriorates due to increased capacitance
Solution Approach 1:
The mandrel is formed in advance with precise dimensions and positioning that define the future air gap characteristics. This preliminary structuring ensures that when the air gap is formed through etching, it automatically inherits the precise geometry needed for optimal capacitance reduction, thereby maintaining operational speed.
Solution Approach 2:
The patent controls the air gap parameters (size, shape, position) by controlling the mandrel parameters. By changing or optimizing mandrel dimensions during fabrication, the resulting air gap parameters are automatically optimized for electrical performance, ensuring low capacitance and high operational speed while maintaining reliability through consistent parameter control.
3Reliability
If conventional via alignment methods are used, then manufacturing process simplicity is maintained, but electrical separation reliability deteriorates due to misalignment
Solution Approach 1:
The mandrel serves as an intermediary reference structure that decouples the alignment relationship between vias and interconnects. Instead of requiring direct alignment between these two features, the mandrel provides a common reference framework, allowing each to be aligned independently to the mandrel, thereby ensuring reliable electrical separation while simplifying the manufacturing process.
Solution Approach 2:
The mandrel is preliminarily formed with alignment marks or reference features that establish a precise coordinate system before other structures are added. This preliminary reference framework enables subsequent alignment operations to be performed relative to the mandrel rather than requiring complex mutual alignment, thereby ensuring reliable electrical separation through consistent positional relationships.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operational speed and stability of the integrated circuit device by maintaining air gaps throughout the interconnects' length, preventing leakage paths and ensuring reliable operation even with misaligned vias, while suppressing corrosion and improving reliability.
Implementation Method 1
forming a first insulating film on a semiconductor substrate; forming a second insulating film on the first insulating film
Implementation Method 2
performing etching under a condition that an etching speed for the first insulating film is higher than an etching speed for the second insulating film
Data Source
AI summary
An integrated circuit device includes a first insulating film, a second insulating film provided on the first insulating film, and having a composition different from a composition of the first insulating film, a first interconnect extending in a first direction crossing a vertical direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film, and a second interconnect extending in the first direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film. An air gap is formed in the first insulating film and in the second insulating film and also between the first interconnect and the second interconnect. A lower end of the air gap is located lower than a lower surface of the first interconnect and a lower surface of the second interconnect.