Air-Gap Isolation Layer for Non-Volatile Memory Parasitic Capacitance
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Solution Overview
Problem
Highly integrated non-volatile memory devices face challenges in reducing parasitic capacitance while maintaining performance, as existing manufacturing methods struggle to achieve both low parasitic capacitance and good reliability.
Innovation Solution
A semiconductor device design featuring a substrate with trenches, gate structures, isolation layers with air gaps, and insulating interlayers, where the isolation layers have air gaps between floating gates to reduce parasitic capacitance, and a manufacturing method that forms these air gaps through sequential layer formation and etching processes to create a dielectric and control gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-volatile memory devices are highly integrated, then device density and capacity are improved, but parasitic capacitance between wirings, gates and active regions increases
Solution Approach 1:
The patent introduces air gaps (porous structures) between adjacent floating gates and between floating gates and active regions. These air gaps act as low-dielectric-constant regions that reduce parasitic capacitance coupling while maintaining the high-density memory structure. The air gaps are formed by removing portions of the dielectric layer to create void spaces that electrically isolate adjacent structures.
Solution Approach 2:
The patent extracts (removes) portions of the dielectric layer to create air gaps in critical locations. By taking out material from the dielectric layer between floating gates and between floating gates and active regions, the patent eliminates the source of parasitic capacitance while preserving the overall device architecture and high-density integration.
2Object-generated harmful factors
If air gaps are introduced to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms the air gap structure during the standard memory fabrication process by selectively removing dielectric material at appropriate stages. The air gaps are created as part of the floating gate formation process, where portions of the dielectric layer are removed before or during floating gate deposition, integrating the parasitic capacitance reduction into the existing manufacturing flow without requiring separate complex processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance between floating gates and active regions, enhancing the reliability and performance of non-volatile memory devices by minimizing interference between adjacent memory cells.
Implementation Method 1
parasitic capacitances between wirings, gates and active regions have been increased
Implementation Method 2
The isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates
Data Source
AI summary
A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.