Non-volatile Memory Air Gap Isolation and Dielectric Coupling
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Solution Overview
Problem
As semiconductor devices continue to shrink, there is a need for increased storage density and reduced parasitic capacitances in non-volatile memory arrays, which existing technologies struggle to achieve due to space limitations and interference between floating gates and control gates.
Innovation Solution
The implementation of a flat memory cell structure with varying dielectric materials and air gaps in both the column and row directions to provide electrical isolation, reducing parasitic capacitances and enhancing coupling between control and floating gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory cell structures are used, then fabrication is simpler, but storage density is lower and parasitic capacitances are higher
Solution Approach 1:
The memory cell structure is segmented into distinct functional regions including charge storage regions, control gate regions, and isolation regions. The isolation regions are further segmented with air gaps positioned between adjacent memory cell strings, creating discrete electrical zones that reduce parasitic coupling while maintaining high density through efficient space utilization.
Solution Approach 2:
The patent introduces vertical stacking of multiple memory cell strings along the column direction, transitioning from planar to three-dimensional architecture. This dimensional change increases storage density by utilizing the vertical space above the substrate, while air gaps between strings provide electrical isolation in the horizontal plane, effectively decoupling the density improvement from parasitic capacitance increase.
2Quantity of substance
If memory cell strings are placed closer together to increase density, then storage capacity increases, but parasitic capacitance between adjacent floating gates and control gates increases
Solution Approach 1:
Air gaps are introduced as intermediary regions between adjacent memory cell strings, positioned within the isolation regions. These air gaps act as electrical mediators that provide isolation between the floating gates and control gates of adjacent strings, reducing parasitic capacitance coupling while allowing the strings to be positioned closely together for high density.
Solution Approach 2:
The patent applies different dielectric properties to different spatial locations: air gaps (vacuum/low dielectric constant) are positioned between adjacent memory cell strings in the column direction to reduce parasitic capacitance, while high-k dielectric materials are positioned between control gates and charge storage regions to enhance coupling. This localized differentiation of dielectric quality optimizes both isolation and coupling requirements simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased storage density and robust performance in non-volatile memory arrays by minimizing interference and optimizing space utilization between memory elements, while maintaining effective electrical isolation.
Implementation Method 1
air gaps in both the column and row directions to provide electrical isolation, reducing parasitic capacitances
Implementation Method 2
a first set of charge storage regions arranged in a column direction and separated from a surface of a substrate by a tunnel dielectric
Implementation Method 3
separated from a first set of control gate regions by a first set of intermediate dielectric regions overlying the first set of charge storage regions
Data Source
AI summary
High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.