Air Gap Isolation for 3D Memory Capacitive Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for manufacturing three-dimensional memory structures, such as vertical NAND strings, face challenges in efficiently forming electrically conductive layers and insulating spacers to achieve optimal electrical isolation and contact configurations, which affect the performance and density of these memory devices.
Innovation Solution
A method involving the formation of alternating layers of sacrificial materials, selective etching, and anisotropic deposition to create electrically conductive layers and insulating spacers with specific geometries, allowing for the formation of backside contact via structures and encapsulated cavities that enhance electrical isolation and mechanical support for the memory stack structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional methods are used to form electrically conductive layers and insulating spacers, then fabrication complexity is reduced, but electrical isolation and capacitive coupling optimization are insufficient
Solution Approach 1:
The method performs preliminary actions by forming the insulating spacer and air gap structures before finalizing the electrically conductive layers. The insulating spacer is deposited and patterned in advance, creating a template that guides subsequent conductive layer formation. This preliminary structuring ensures optimal electrical isolation is built into the architecture before conductive elements are added, preventing later isolation issues without requiring complex post-processing steps.
Solution Approach 2:
The fabrication process is segmented into distinct sequential steps: first forming the insulating spacer, then creating air gaps through selective removal, and finally depositing electrically conductive layers in specific regions. This segmentation allows each structure to be optimized independently - the insulating spacer for electrical isolation, the air gaps for capacitive coupling control, and the conductive layers for electrical connectivity - thereby achieving high reliability without overwhelming fabrication complexity.
2Reliability
If air gap isolation structures are implemented, then capacitive coupling between conductive layers is reduced, but fabrication process complexity increases
Solution Approach 1:
The method extracts material to create air gaps by selectively removing portions of previously deposited layers. After forming the insulating spacer, specific regions are etched away to create voids that serve as air gap isolation structures. This extraction approach is simpler than attempting to deposit complex three-dimensional air gap structures directly, as it uses standard etching processes to remove material and create the desired isolation regions between conductive layers.
Solution Approach 2:
The air gap structures are formed by transitioning from two-dimensional layer deposition to three-dimensional void creation. The insulating spacer provides vertical isolation, while the air gaps introduce horizontal isolation dimensions. This multi-dimensional approach to isolation - combining vertical spacer structures with horizontal air gap regions - achieves superior capacitive coupling control without requiring equally complex three-dimensional fabrication techniques.
3Manufacturing precision
If selective material removal and anisotropic deposition are used, then manufacturing precision of conductive layer geometries is improved, but production time increases
Solution Approach 1:
The insulating spacer is formed in advance with precise geometric control through anisotropic deposition, establishing a template that defines the geometry of subsequent conductive layers. This preliminary precision work reduces the need for complex alignment and patterning steps later, as the pre-formed spacer acts as a self-aligning mask and structural guide, thereby maintaining manufacturing precision while reducing overall production time.
Solution Approach 2:
The anisotropically deposited insulating spacer structure serves as its own patterning template for subsequent conductive layer formation. The spacer's geometric features automatically define where conductive materials should be deposited and where air gaps should exist, eliminating the need for separate photolithography and etching steps to create these patterns. This self-service approach maintains high manufacturing precision while streamlining the fabrication process and reducing production time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of monolithic three-dimensional memory devices with improved electrical isolation, reduced capacitive coupling between conductive layers, and simplified fabrication, leading to increased memory density and performance.
Implementation Method 1
A dielectric material is deposited over a sidewall of the trench and first portions of the horizontal surfaces of the electrically conductive layers that are proximal to the trench to form a contiguous dielectric material layer while not depositing the dielectric material over second portions of the horizontal surfaces of the electrically conductive layers that are more distal from the trench than the first portions
Implementation Method 2
An insulating spacer is formed in the trench by anisotropically etching the contiguous dielectric material layer
Data Source
AI summary
Electrically conductive layers for control gate electrodes of a vertical memory device can be vertically spaced by cavities to reduce capacitive coupling between neighboring electrically conductive gate electrodes. An alternating stack of first material layers and second material layers can be provided. After replacing the second material layers with electrically conductive layers, the first material layers can be removed to form cavities between the electrically conductive layers. A dielectric material can be deposited with high anisotropic deposition rate to form an insulating spacer. For example, a plasma assisted atomic layer deposition process can be employed to deposit a dielectric spacer that include laterally protruding portions that encapsulate the cavities at each level between neighboring pairs of electrically conductive layers. A contact via structure can be formed in the insulating spacer to provide electrical contact to a source region.