Air Gap Isolation and Carbon Masking for NAND Flash Memory
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Solution Overview
Problem
The challenge in manufacturing NAND-type flash memory devices is to reduce the space between gate electrodes while maintaining a sufficient process margin for forming electrical contacts and minimizing capacitance between wirings and substrates, which degrades device operation.
Innovation Solution
A method involving the formation of air gaps in element isolation regions and between gate electrodes, using carbon side walls as a mask for impurity ion implantation, and careful etching to secure process margins for contact formation, thereby reducing capacitance and preventing excessive etching of element isolation insulating films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the space between gate electrodes of adjacent select gate transistors is reduced to achieve higher density, then memory cell density is improved, but the process margin for forming electrical contacts deteriorates
Solution Approach 1:
The patent divides the isolation structure into multiple segments: air gaps are formed in element isolation regions between memory cell transistors, while a insulating film is maintained in the select gate transistor region. This segmentation allows different spacing configurations in different areas, enabling high density in memory cells while preserving contact formation margin in select gate regions.
Solution Approach 2:
The patent applies different isolation qualities to different locations: air gaps (vacuum isolation) are created in element isolation regions to minimize capacitance, while a solid insulating film is retained in the select gate transistor region to ensure sufficient process margin for electrical contact formation. This local differentiation resolves the contradiction between density and manufacturing precision.
2Reliability
If air gaps are formed in element isolation regions to reduce capacitance, then device operation is improved, but the process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the air gaps in element isolation regions before forming the select gate transistor structures. The insulating film is selectively removed from element isolation regions at an early stage, creating air gaps that reduce capacitance. Subsequent processing steps then form select gate transistors with preserved process margins, making the overall process more manageable despite the added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reduction of capacitance and interference between memory cells, ensuring stable device operation and enabling higher density memory cell arrays with improved contact formation margins.
Implementation Method 1
forming carbon side walls on the select gate electrodes; implanting ions of an impurity into the element regions between the two select gate electrodes with the carbon side walls as a mask
Implementation Method 2
forming air gaps in element isolation regions and between the gate electrodes... the capacitance between wirings, substrates, or between the wiring and the substrate within the memory cell array may cause a problem of degradation in device operation
Implementation Method 3
etching the first insulating film, after forming the memory cell gate electrodes, so that the first insulating film remains in at least the element isolation region of a region in which a select gate electrode is to be formed
Data Source
AI summary
A method of manufacturing a non-volatile semiconductor memory device of an embodiment includes: forming, on a semiconductor substrate, an element isolation region to be filled with a first insulating film; forming memory cell gate electrodes on element regions; etching the first insulating film so that the first insulating film remains in the element isolation region of a region in which a select gate electrode is to be formed; forming a second insulating film on the memory cell gate electrodes so that an air gap is created between the memory cell gate electrodes; forming two select gate electrodes; forming carbon side walls on the select gate electrodes; implanting ions of an impurity between the two select gate electrodes with the side walls as a mask; and removing the carbon side walls.