Air Gap Isolation for Non-Volatile Memory Density
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Solution Overview
Problem
As semiconductor memory devices evolve to increase storage density, they face challenges in electrical isolation between closely spaced components, leading to parasitic interferences and charge transfer issues, particularly in NAND flash arrays with small feature sizes.
Innovation Solution
The introduction of air gaps in both the column (bit line) and row (word line) directions within the memory structure provides electrical isolation between adjacent components, utilizing high dielectric constant materials and self-aligned high-K approaches to reduce parasitic capacitances and charge transfer, while incorporating thin metal/charge-trap floating gates to address ballistic charge programming concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If components are closely spaced to increase storage density, then storage density is improved, but parasitic interferences and charge transfer issues worsen
Solution Approach 1:
The patent introduces air gaps that segment the continuous dielectric material into isolated regions between adjacent memory strings. This segmentation creates physical separation that reduces parasitic capacitance and charge transfer between closely spaced components, allowing higher storage density without the harmful side effects of component crowding
Solution Approach 2:
The air gap acts as an intermediary layer between adjacent memory strings and their associated control gates. This intermediate air region provides electrical isolation that prevents direct charge transfer and reduces parasitic coupling, enabling components to be placed closer together while maintaining signal integrity
2Object-generated harmful factors
If air gaps are introduced to reduce parasitic capacitances, then parasitic interferences are decreased, but fabrication complexity increases
Solution Approach 1:
The fabrication process uses self-aligned spacer formation where the air gaps are automatically positioned relative to the control gates and memory strings. The spacer material is deposited conformally and then anisotropically etched back, creating air gaps that are self-aligned to the underlying structures without requiring additional alignment steps, thus reducing fabrication complexity despite the added structural element
Solution Approach 2:
The patent modifies the dielectric constant parameter by introducing air (εr≈1) regions between the solid dielectric materials. This parameter change fundamentally reduces parasitic capacitance since capacitance is directly proportional to the dielectric constant of the material between conductors, achieving the desired electrical isolation through material parameter selection rather than complex geometric arrangements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively decreases parasitic interferences and enhances coupling between control gates and floating gates, improving the isolation and operational efficiency of non-volatile memory arrays, thereby increasing storage density and reducing fabrication complexities.
Implementation Method 1
The introduction of air gaps in both the column (bit line) and row (word line) directions within the memory structure provides electrical isolation between adjacent components, utilizing high dielectric constant materials and self-aligned high-K approaches to reduce parasitic capacitances and charge transfer
Implementation Method 2
utilizing high dielectric constant materials and self-aligned high-K approaches to reduce parasitic capacitances and charge transfer, while incorporating thin metal/charge-trap floating gates to address ballistic charge programming concerns
Data Source
AI summary
Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.