Air Gap Isolation Trench for Floating Gate Semiconductor Devices
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing power consumption and improving data retention characteristics while maintaining operating speed, particularly in mobile devices, due to limitations in isolating floating gate electrodes and tunneling insulating layers.
Innovation Solution
A semiconductor device is designed with tunneling insulating layers on active regions of a substrate, floating gate electrodes, and an isolation trench that includes an air gap, with specific insulating layers configured to hermetically seal the trench and reduce electrical interference, using materials like silicon oxide, silicon nitride, and metal oxide to optimize dielectric constants and energy bandgaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional insulating materials and structures are used to isolate floating gate electrodes, then manufacturing is simpler, but parasitic capacitance and charge leakage increase, reducing data retention and increasing power consumption
Solution Approach 1:
The patent changes the physical parameters of the isolation trench by introducing an air gap (vacuum/air-filled space) instead of filling it with conventional insulating material. This parameter change reduces the dielectric constant from typical insulator values (3-10) to approximately 1 for air/vacuum, thereby reducing parasitic capacitance between adjacent floating gate electrodes and improving data retention while reducing power consumption.
Solution Approach 2:
The patent extracts the insulating material from the isolation trench and replaces it with an air gap. By removing the solid insulating material and creating a vacuum or air-filled space, the patent eliminates the source of parasitic capacitance while maintaining electrical isolation, directly addressing the contradiction between reliability and power consumption.
2Reliability
If air gap is introduced in isolation trench to reduce parasitic capacitance, then data retention improves, but manufacturing complexity increases due to hermetic sealing requirements
Solution Approach 1:
The patent applies preliminary action by forming the air gap structure during the trench formation process itself, rather than attempting to create it afterward. The trench is etched to the appropriate depth and shape in advance, and the air gap is established as part of the initial isolation structure, simplifying subsequent manufacturing steps while maintaining the reliability benefits.
Solution Approach 2:
The patent uses thin film insulating layers (such as oxide or nitride layers) to hermetically seal the air gap in the isolation trench. These thin films provide effective sealing against contamination while maintaining the low-dielectric-constant environment, balancing the need for hermetic sealing with manufacturing feasibility.
3Reliability
If isolation trench depth is increased to improve electrical isolation, then charge leakage decreases, but manufacturing precision requirements increase and parasitic capacitance reduction is limited
Solution Approach 1:
The patent changes the critical parameter from trench depth to trench width and air gap configuration. By optimizing the horizontal dimensions and creating an air-filled space, the patent achieves effective electrical isolation without requiring extremely deep trenches, thereby reducing manufacturing precision requirements while maintaining reliable charge isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and charge leakage, enhancing data retention and reducing power consumption while maintaining high operating speeds, thereby improving the performance and efficiency of semiconductor devices.
Implementation Method 1
A dielectric constant of the middle insulating layer may be greater than a dielectric constant of the lower insulating layer
Implementation Method 2
An energy bandgap of the upper insulating layer may be greater than an energy bandgap of the middle insulating layer
Data Source
AI summary
A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.