Air-Gap Conductive Line Layout for Lower 3D NAND Capacitance

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Solution Overview

Problem

As memory devices, such as 3D NAND Flash memory devices, experience increased parasitic capacitance due to decreasing dimensions and spacing of conductive features, leading to higher power demands and delays, air gaps are introduced to electrically isolate conductive lines.

Innovation Solution

Formation of air gaps laterally adjacent to conductive lines, extending above and below the plane of the conductive lines, reduces parasitic capacitance by using a subtractive patterning process and a single damascene process to form interconnect structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the dimensions and spacing of conductive features are decreased to increase memory density, then memory density is improved, but parasitic capacitance increases leading to higher power demands and delays

Engineering Contradiction:
Improvememory densityVSAvoidpower demand
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

An air gap structure is introduced as an intermediary between adjacent conductive lines to reduce parasitic capacitance. The air gap acts as a dielectric medium with lower permittivity than traditional insulating materials, thereby reducing the capacitive coupling between conductive features while maintaining their close spacing for high density

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric parameter (permittivity) between conductive lines is changed from traditional insulating materials to air (vacuum), which has a permittivity of approximately 8.85×10^-12 F/m. This parameter change directly reduces the parasitic capacitance value, lowering power consumption and signal delay while maintaining the reduced dimensions and spacing of conductive features

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If air gaps are introduced to reduce parasitic capacitance, then power consumption is reduced, but device fabrication complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidfabrication complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The formation of air gaps is merged with the existing conductive line formation process. The same patterning and etching steps used to create conductive lines are also used to define the air gap regions, eliminating the need for separate air gap formation processes and reducing overall fabrication complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The air gap structure serves multiple functions simultaneously: it acts as an electrical insulator to reduce parasitic capacitance, defines the spacing between conductive lines for high density, and is formed using the same process steps as the conductive lines themselves, making it a multi-functional element in the device architecture

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12593679B2Apparatuses and memory devices including air gaps between conductive lines
Publication Date: 2026.03.31 MICRON TECHNOLOGY INC
  • US12593679B2 patent drawing
  • US12593679B2 patent drawing
  • US12593679B2 patent drawing

AI summary

A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.